公开(公告)号：US20230380158A1

公开(公告)日：2023-11-23

申请号：US17746202

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions and a through-array-via (TAV) region. The stack comprises channel-material strings extending through the first tiers and the second tiers. The stack comprises horizontally-elongated trenches extending through the first tiers and the second tiers and that are individually between immediately-laterally-adjacent of the memory-block regions. The stack comprises TAV openings in the TAV region. Conductive material is formed in the TAV openings and in the horizontally-elongated trenches at the same time. All of the conductive material is removed from the horizontally-elongated trenches while leaving the conductive material in the TAV openings to comprise TAVs therein in a finished circuitry construction. After the removing, intervening material is formed in the horizontally-elongated trenches. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230377653A1

公开(公告)日：2023-11-23

申请号：US17747166

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion directly above a lower portion. The upper portion comprises vertically-alternating tiers that are of different composition relative one another. The lower portion comprises dummy plugs that comprise metal oxide directly above metal material. The metal oxide and the metal material comprise different compositions relative one another. Other embodiments, including method, are disclosed.

公开(公告)号：US11805651B2

公开(公告)日：2023-10-31

申请号：US17854393

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H10B43/27 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02636 ,  H01L21/31111 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230307368A1

公开(公告)日：2023-09-28

申请号：US17702160

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through a lowest of the conductive tiers. The TAV constructions individually comprise an insulative lining having a lowest surface that is directly against metal material in the lowest conductive tier. Other embodiments, including method, are disclosed.

公开(公告)号：US20230290860A1

公开(公告)日：2023-09-14

申请号：US18200153

申请日：2023-05-22

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins

IPC: H01L29/66 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/66545 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier. The conducting material less-than-fills the void-space in the lowest first tier. The conducting material is etched from the lowest first tier. After the etching of the conducting material, conductive material is deposited into the void-space of the lowest first tier and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Additional embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11744069B2

公开(公告)日：2023-08-29

申请号：US17030751

申请日：2020-09-24

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/311 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/31116 ,  H10B43/10

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier. The immediately-adjacent tier comprises material that is of different composition from that of the lowest insulator tier. Other embodiments, including methods, are disclosed.

公开(公告)号：US20230262978A1

公开(公告)日：2023-08-17

申请号：US17674219

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tiers. A void space is formed directly above the conductor tier laterally-across individual of the memory-block regions. The void space comprises an exposed silicon-containing surface. Conductively-doped silicon is selectively deposited onto and from the exposed silicon-containing surface. The conductively-doped silicon is directly electrically coupled to the channel material of the channel-material strings and is directly electrically coupled to the conductor material of the conductor tier and directly electrically couples the channel-material strings to the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11716848B2

公开(公告)日：2023-08-01

申请号：US17126777

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/40 ,  H10B43/50

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230114572A1

公开(公告)日：2023-04-13

申请号：US18080382

申请日：2022-12-13

Applicant: Micron Technology, Inc

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L29/788 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11594495B2

公开(公告)日：2023-02-28

申请号：US17209993

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.