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    Apparatuses including electrodes having a conductive barrier material and methods of forming same
    21.
    发明授权
    Apparatuses including electrodes having a conductive barrier material and methods of forming same 有权

    公开(公告)号：US10651381B2

    公开(公告)日：2020-05-12

    申请号：US16040515

    申请日：2018-07-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Swapnil A. Lengade ,  John M. Meldrim ,  Andrea Gotti

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.

    Memory Arrays and Methods of Fabricating Integrated Structures
    28.
    发明申请
    Memory Arrays and Methods of Fabricating Integrated Structures 有权
    内存阵列和制造集成结构的方法

    公开(公告)号：US20160172373A1

    公开(公告)日：2016-06-16

    申请号：US15049097

    申请日：2016-02-21

    Applicant: Micron Technology, Inc.

    Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

    Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

    Memory arrays
    29.
    发明授权
    Memory arrays 有权
    内存阵列

    公开(公告)号：US09287379B2

    公开(公告)日：2016-03-15

    申请号：US14281569

    申请日：2014-05-19

    Applicant: Micron Technology, Inc.

    Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

    IPC: H01L27/115 ,  H01L29/49 ,  H01L21/28

    CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

    Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

    METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES
    30.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES 有权
    制作半导体结构的方法

    公开(公告)号：US20150011063A1

    公开(公告)日：2015-01-08

    申请号：US14494175

    申请日：2014-09-23

    Applicant: Micron Technology, Inc.

    Inventor： Jeffery B. Hull ,  John M. Meldrim

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

    CPC classification number: H01L29/66825 ,  H01L21/02178 ,  H01L21/28035 ,  H01L21/31111 ,  H01L27/11556 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7889

    Abstract: Semiconductor structures including an etch stop material between a substrate and a stack of alternating insulating materials and first conductive materials, wherein the etch stop material comprises an amorphous aluminum oxide on the substrate and a crystalline aluminum oxide on the amorphous aluminum oxide; a channel material extending through the stack; and a second conductive material between the channel material and at least one of the first conductive materials in the stack of alternating insulating materials and first conductive materials, wherein the second conductive material is not between the channel material and the etch stop material. Also disclosed are methods of fabricating such semiconductor structures.

    Abstract translation: 半导体结构包括在衬底和交替绝缘材料和第一导电材料的堆叠之间的蚀刻停止材料，其中所述蚀刻停止材料包括在所述衬底上的无定形氧化铝和所述非晶态氧化铝上的结晶氧化铝; 延伸穿过堆叠的通道材料; 以及在所述沟道材料和交替绝缘材料和第一导电材料的堆叠中的所述第一导电材料中的至少一个之间的第二导电材料，其中所述第二导电材料不在所述沟道材料和所述蚀刻停止材料之间。 还公开了制造这种半导体结构的方法。

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