公开(公告)号：US20190317545A1

公开(公告)日：2019-10-17

申请号：US16448297

申请日：2019-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G06F1/06 ,  G06F1/12 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10 ,  G11C19/00 ,  G11C11/408 ,  G11C11/4093 ,  G11C7/22 ,  G11C7/00

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US10090026B2

公开(公告)日：2018-10-02

申请号：US15445795

申请日：2017-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G06F1/12 ,  G11C11/4093 ,  G11C7/10 ,  G11C19/00

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US09508417B2

公开(公告)日：2016-11-29

申请号：US14185194

申请日：2014-02-20

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C2207/2272

Abstract: Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An example apparatus may include a timing circuit. The timing circuit may be configured to provide a clock signal to the forward path, adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal, select a feedback clock signal responsive to a loop delay of the timing circuit, and provide a control signal to an adjustable delay circuit of the forward path circuit. Another example apparatus may include a forward path configured to delay a signal based at least in part on a loop delay and a latency value, and a latency control circuit configured to provide an adjusted latency value as the latency value responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command.

Abstract translation: 这里描述了用于在时钟频率变化（例如减速模式）期间控制定时电路锁定和/或等待时间的装置和方法。 示例性装置可以包括定时电路。 定时电路可以被配置为向正向路径提供时钟信号，响应于接收到调整时钟信号速率的命令来调整时钟信号的速率，响应于所述时钟信号的环路延迟选择反馈时钟信号 定时电路，并向前向路径电路的可调延迟电路提供控制信号。 另一个示例性装置可以包括被配置为至少部分地基于环路延迟和等待时间值来延迟信号的前向路径，以及延迟控制电路，被配置为响应于接收到命令而提供调整后的等待时间值作为等待时间值， 其中所述前向路径被配置为响应于所述命令的接收至少部分地以调整的时钟速率运行。

公开(公告)号：US09087570B2

公开(公告)日：2015-07-21

申请号：US13744177

申请日：2013-01-17

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P Wright

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

Abstract translation: 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。

公开(公告)号：US20150130521A1

公开(公告)日：2015-05-14

申请号：US14599265

申请日：2015-01-16

Applicant: Micron Technology, Inc.

Inventor： Tyler Gomm ,  Kang Yong Kim ,  Scott Smith ,  Jongtae Kwak

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0802 ,  H03L7/0812 ,  H03L7/095

Abstract: Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.

Abstract translation: 描述了用于检测时钟同步电路的锁定或同步状态的锁定状态检测电路，设备，系统和方法。 检测锁定状态包括电路，该电路包括相位检测器，该相位检测器被配置为响应于表示外部时钟信号的前向路径信号与表示输出时钟信号的反馈路径信号的比较而产生延迟调整信号。 电路还包括可操作地耦合到延迟调整信号并被配置为产生指示外部时钟信号和输出时钟信号之间的同相稳态的锁定信号的趋势检测器。

公开(公告)号：US20150049558A1

公开(公告)日：2015-02-19

申请号：US14530911

申请日：2014-11-03

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/106 ,  G11C7/1018 ,  G11C7/1066 ,  G11C7/222

Abstract: A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

Abstract translation: 用于控制动态突发长度控制数据的存储器，系统和方法可以通过使用基本上相同的等待时间延迟的接收命令指示来为上游计数器和下游计数器产生时钟。 下行时钟产生电路从延迟锁定环路延迟的接收到的命令指示和等待时间控制电路中存储的等待时延延迟生成时钟信号。 上行时钟发生电路根据延迟锁定环延迟的接收命令指示产生时钟信号，并从等待时间控制电路捕获指示。

公开(公告)号：US20140198591A1

公开(公告)日：2014-07-17

申请号：US13744177

申请日：2013-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

Abstract translation: 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。

公开(公告)号：US20140035640A1

公开(公告)日：2014-02-06

申请号：US14046796

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak ,  Kallol Mazumder

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0816

Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.

Abstract translation: 公开了与改变用于执行命令的命令信号的定时相关的装置和方法。 一种这样的方法包括根据由时钟电路提供的输出时钟信号的时钟周期的数量来计算时钟电路的前向路径延迟，并将多个延迟的附加时钟周期与信号路径的前向路径延迟相加 。 时钟电路的正向路径延迟表示信号路径的前向路径延迟，并且附加时钟周期的数量至少部分地基于前向路径延迟的时钟周期数。

公开(公告)号：US11675662B2

公开(公告)日：2023-06-13

申请号：US17348211

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

CPC classification number: G06F11/1072 ,  G06F11/1012 ,  G06F11/1052 ,  G11C7/1018

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US11514977B2

公开(公告)日：2022-11-29

申请号：US17220110

申请日：2021-04-01

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Jongtae Kwak

IPC: G11C29/00 ,  G11C11/4094 ,  G11C29/44 ,  G06F11/10 ,  G11C11/408

Abstract: Memory device data-access schemes are disclosed. Various embodiments may include a memory device including a first column plane, a second column plane, and a data-steering circuit. The first column plane may include a first edge, a second edge, and a first number of digit lines arranged between the first edge and the second edge. The second column plane may include a third edge positioned adjacent to the second edge, a fourth edge, and a second number of digit lines arranged between the third edge and the fourth edge. The data-steering circuit may be configured to logically relate a first digit line of the first number of digit lines to a second digit line of the second number of digit lines, the first digit line proximate to the first edge and the second digit line proximate to the fourth edge. Associated systems and methods are also disclosed.