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    Apparatuses and methods for die seal crack detection
    22.
    发明授权
    Apparatuses and methods for die seal crack detection 有权
    模具密封裂纹检测的装置和方法

    公开(公告)号：US09287184B2

    公开(公告)日：2016-03-15

    申请号：US14106190

    申请日：2013-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

    IPC: H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L29/78

    CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

    Abstract translation: 设备和方法可以包括在管芯的集成电路区域和管芯周边之间的管芯密封。 通孔链可围绕模具密封件和集成电路区域之间的模具密封件的内圆周和/或围绕模具密封件和模具周边之间的模具密封件的外圆周布置。 通孔链可以包括多个由导电材料组成并且延伸穿过模具的部分的触点。 电路可以耦合到通孔链的端部以检测电信号。 描述附加的装置和方法。

    PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS
    24.
    发明申请
    PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS 有权
    具有嵌入式泄漏检查的程序操作

    公开(公告)号：US20150364213A1

    公开(公告)日：2015-12-17

    申请号：US14302782

    申请日：2014-06-12

    Applicant: Micron Technology, Inc.

    Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

    IPC: G11C29/04 ,  G11C16/10 ,  G01R31/02

    CPC classification number: G11C16/3459 ,  G01R31/02 ,  G11C7/00 ,  G11C7/02 ,  G11C8/08 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/02 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5006

    Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

    Abstract translation: 操作具有嵌入式泄漏检查的存储器件的方法可以减轻由于存取线缺陷引起的数据丢失事件，并且可以促进改进的功耗特性。 这样的方法可以包括将程序脉冲施加到被选择用于编程的存储器单元的选定访问线，验证所选择的存储单元是否已经达到期望的数据状态，将所选择的访问线路施加到第一电压，将第二电压施加到 未选择的接入线路，将参考电流施加到所选择的接入线路，以及确定所选择的接入线路与未选择接入线路之间的当前流量是否大于参考电流。

    Memory system failure detection and self recovery of memory dice
    25.
    发明授权
    Memory system failure detection and self recovery of memory dice 有权

    公开(公告)号：US12229024B2

    公开(公告)日：2025-02-18

    申请号：US18608652

    申请日：2024-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Robert Mason ,  Scott A. Stoller ,  Pitamber Shukla ,  Kenneth W. Marr ,  Chi Ming Chu ,  Hossein Afkhami

    IPC: G06F11/14 ,  G06F9/30

    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

    MANAGING TRAP-UP IN A MEMORY SYSTEM
    26.
    发明公开
    MANAGING TRAP-UP IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240233842A1

    公开(公告)日：2024-07-11

    申请号：US18393354

    申请日：2023-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla ,  Chi Ming W. Chu ,  Avinash Rajagiri ,  Ching-Huang Lu ,  Kenneth W. Marr

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/28

    CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3404

    Abstract: Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.

    MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE
    27.
    发明公开
    MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE 审中-公开

    公开(公告)号：US20240220375A1

    公开(公告)日：2024-07-04

    申请号：US18608652

    申请日：2024-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Robert Mason ,  Scott A. Stoller ,  Pitamber Shukla ,  Kenneth W. Marr ,  Chi Ming Chu ,  Hossein Afkhami

    IPC: G06F11/14 ,  G06F9/30

    CPC classification number: G06F11/1471 ,  G06F9/30098 ,  G06F11/1469

    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

    Memory system failure detection and self recovery of memory dice
    28.
    发明授权
    Memory system failure detection and self recovery of memory dice 有权

    公开(公告)号：US11966303B2

    公开(公告)日：2024-04-23

    申请号：US17877779

    申请日：2022-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Robert Mason ,  Scott A. Stoller ,  Pitamber Shukla ,  Kenneth W. Marr ,  Chi Ming Chu ,  Hossein Afkhami

    IPC: G06F11/14 ,  G06F9/30

    CPC classification number: G06F11/1471 ,  G06F9/30098 ,  G06F11/1469

    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

    Active protection circuits for semiconductor devices
    29.
    发明授权
    Active protection circuits for semiconductor devices 有权

    公开(公告)号：US11676917B2

    公开(公告)日：2023-06-13

    申请号：US17103447

    申请日：2020-11-24

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Kenneth W. Marr

    IPC: H01L23/60 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11529

    CPC classification number: H01L23/60 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

    Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

    ACTIVE PROTECTION CIRCUITS FOR SEMICONDUCTOR DEVICES
    30.
    发明申请
    ACTIVE PROTECTION CIRCUITS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220165688A1

    公开(公告)日：2022-05-26

    申请号：US17103447

    申请日：2020-11-24

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Kenneth W. Marr

    IPC: H01L23/60 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

    Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

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