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公开(公告)号：US11481273B2
公开(公告)日：2022-10-25
申请号：US16995359
申请日：2020-08-17
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo′ Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.
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公开(公告)号：US20220291865A1
公开(公告)日：2022-09-15
申请号：US17829861
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.
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公开(公告)号：US20220215895A1
公开(公告)日：2022-07-07
申请号：US17700085
申请日：2022-03-21
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
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公开(公告)号：US20220181341A1
公开(公告)日：2022-06-09
申请号：US17110439
申请日：2020-12-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Haitao Liu , Michael Violette , Mark A. Helm , Guangyu Huang , Vladimir Mikhalev
IPC: H01L27/11556 , H01L27/11582 , H01L29/417 , H01L29/78 , H01L27/088 , G11C16/04
Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.
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公开(公告)号：US11288160B2
公开(公告)日：2022-03-29
申请号：US16995246
申请日：2020-08-17
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil, Jr. , Niccolo′ Righetti , Kishore K. Muchherla , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.
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Patent Agency Ranking
公开(公告)号：US20220057944A1
公开(公告)日：2022-02-24
申请号：US17001121
申请日：2020-08-24
Applicant: Micron Technology, Inc.
Inventor： Jeremy Binfet , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Kishore K. Muchherla , Carmine Miccoli , Giuseppina Puzzilli
IPC: G06F3/06
Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device is further coupled to the processing device and to a primary power supply and a secondary power supply. The processing device is to determine, based at least in part on availability of the primary power supply to the memory device, whether to operate the memory device with a first trim tailored to data reliability or a second trim tailored to programming time. The processing device is further to operate the memory device with the determined one of the first trim or the second trim.
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公开(公告)号：US20210349662A1
公开(公告)日：2021-11-11
申请号：US16868868
申请日：2020-05-07
Applicant: Micron Technology, Inc.
Inventor： Mark A. Helm
IPC: G06F3/06
Abstract: Systems and methods are disclosed including a memory component and a processing device, coupled to the memory component. The processing device can program a block of the memory component using a first type of memory cells storing a first number of bits per memory cell. The processing device can then determine that an amount of memory used of the memory component is greater than a capacity threshold. Responsive to determining that a frequency of access to the block meets a criterion, the processing device can then program the block using a second type memory cells storing a second number of bits per memory cell, wherein the second number of bits exceeds the first number of bits.
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28.发明授权公开(公告)号：US10891191B2
公开(公告)日：2021-01-12
申请号：US16352530
申请日：2019-03-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Patrick R. Khayat , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Mark A. Helm , Aaron S. Yip
IPC: G06F11/00 , G06F11/10 , H03M13/37 , H03M13/00 , G11C7/08 , G06F3/06 , G11C16/08 , G11C16/26 , G11C29/52 , H03M13/11 , G11C29/04 , H03M13/29 , G11C11/56 , G11C16/04
Abstract: An example method for determining likelihood of erroneous data bits stored in memory cells may include sensing a first plurality of memory cells based on a first sense thresholds. Responsive to sensing the first plurality of cells, a first set of probabilistic information may be associated with the first plurality of memory cells. A second plurality of memory cells may be sensed based on a second sense threshold. Responsive to sensing the second plurality of memory cells, a second set of probabilistic information may be associated with the second plurality of memory cells. An error correction operation may be performed on the first and second pluralities of memory cells based, at least in part, on the first and second values.
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公开(公告)号：US10115457B2
公开(公告)日：2018-10-30
申请号：US15444982
申请日：2017-02-28
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang , Feng Pan , Ramin Ghodsi , Mark A. Helm
Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
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30.发明申请公开(公告)号：US20180081753A1
公开(公告)日：2018-03-22
申请号：US15267844
申请日：2016-09-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Patrick R. Khayat , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Mark A. Helm , Aaron S. Yip
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C16/08 , G11C16/26 , G11C29/52 , G11C2029/0411 , H03M13/1111 , H03M13/1177 , H03M13/2909 , H03M13/3723 , H03M13/612
Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.
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