公开(公告)号：US11557369B2

公开(公告)日：2023-01-17

申请号：US17221108

申请日：2021-04-02

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Peng Zhao

IPC: G11C29/00 ,  G11C29/50 ,  G11C13/00

Abstract: A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting only one memory element of the plurality of memory elements, determines a second location of the defect when the defect is affecting two or more memory elements of the plurality of memory elements, and performs a blown operation on a defective memory element at the second location when the defect is affecting two or more memory elements of the plurality of memory elements.

公开(公告)号：US20220366224A1

公开(公告)日：2022-11-17

申请号：US17319765

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Dmitry Vengertsev ,  Seth A. Eichmeyer ,  Jing Gong ,  John Christopher M. Sancon ,  Nicola Ciocchini ,  Tom Tangelder

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

Abstract: Apparatuses and methods can be related to implementing a binary neural network in memory. A binary neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the binary neural network and perform operations consistent with the binary neural network. The weights of the binary neural network can correspond to non-zero values.

公开(公告)号：US12277984B2

公开(公告)日：2025-04-15

申请号：US18231514

申请日：2023-08-08

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Nicola Ciocchini

IPC: G11C29/32 ,  G06F3/06 ,  G06F11/07 ,  G11C16/34 ,  G11C29/50 ,  G11C29/52 ,  G11C29/56

Abstract: A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.

公开(公告)号：US20250014655A1

公开(公告)日：2025-01-09

申请号：US18895236

申请日：2024-09-24

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Animesh R. Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Jonathan S. Parry

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.

公开(公告)号：US20240161838A1

公开(公告)日：2024-05-16

申请号：US18505855

申请日：2023-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo’ Righetti ,  Jonathan S. Parry ,  Ugo Russo

IPC: G11C16/34 ,  G11C7/04 ,  G11C16/32

CPC classification number: G11C16/3431 ,  G11C7/04 ,  G11C16/32

Abstract: A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.

公开(公告)号：US11922029B2

公开(公告)日：2024-03-05

申请号：US17863000

申请日：2022-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Jonathan S. Parry ,  Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Ugo Russo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

公开(公告)号：US20230393756A1

公开(公告)日：2023-12-07

申请号：US17863000

申请日：2022-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Jonathan S. Parry ,  Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Ugo Russo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0653

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

公开(公告)号：US20220319629A1

公开(公告)日：2022-10-06

申请号：US17221108

申请日：2021-04-02

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Peng Zhao

IPC: G11C29/50 ,  G11C13/00

Abstract: A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting only one memory element of the plurality of memory elements, determines a second location of the defect when the defect is affecting two or more memory elements of the plurality of memory elements, and performs a blown operation on a defective memory element at the second location when the defect is affecting two or more memory elements of the plurality of memory elements.

公开(公告)号：US11373705B2

公开(公告)日：2022-06-28

申请号：US17101846

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Andrea Gotti

IPC: G11C13/00 ,  H01L45/00

Abstract: Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.

公开(公告)号：US09990990B2

公开(公告)日：2018-06-05

申请号：US14535099

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Paolo Fantini ,  Daniele Ielmini ,  Nicola Ciocchini

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/76

Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.