公开(公告)号：US09666801B2

公开(公告)日：2017-05-30

申请号：US15156105

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

公开(公告)号：US20160027883A1

公开(公告)日：2016-01-28

申请号：US14875497

申请日：2015-10-05

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L29/423 ,  H01L21/288 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/02068 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/316 ,  H01L29/7881

Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.

公开(公告)号：US09153485B2

公开(公告)日：2015-10-06

申请号：US14258885

申请日：2014-04-22

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha ,  Gurtej S. Sandhu

IPC: C23F3/00 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867

Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

Abstract translation: 公开的实施例包括处理衬底的方法，包括形成与衬底的导电连接的方法。 在一个实施例中，处理衬底的方法包括在衬底的第一材料上形成待蚀刻的材料。 待蚀刻的材料和第一种材料具有不同的组成。 待蚀刻的材料在干蚀刻室中蚀刻以暴露第一材料。 在蚀刻之后，第一材料在干蚀刻室内原位与非含氧气体接触，有效地形成物理接触第一材料的第二材料。 第二材料包括第一材料的组分和气体的组分。 在一个实施方案中，第一材料与可在干蚀刻室内原位包含氧的气​​体接触，有效地形成导电的第二材料。

公开(公告)号：US09147691B2

公开(公告)日：2015-09-29

申请号：US14274933

申请日：2014-05-12

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L27/115 ,  H01L21/311 ,  H01L27/06 ,  H01L29/788 ,  H01L29/786

CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0688 ,  H01L29/78642 ,  H01L29/7889

Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

Abstract translation: 描述制造多层半导体器件的方法以及包括它们的装置和系统。 在一种这样的方法中，形成第一电介质，并且形成与第一电介质接触的第二电介质。 通过第一电介质和第二电介质通过第一蚀刻化学品形成通道，在第一电介质中用第二蚀刻化学物质形成空隙，并且器件至少部分地形成在第一电介质的空隙中。 还描述了另外的实施例。

公开(公告)号：US20190363253A1

公开(公告)日：2019-11-28

申请号：US16538477

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

公开(公告)号：US10411186B2

公开(公告)日：2019-09-10

申请号：US15848399

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

公开(公告)号：US09865812B2

公开(公告)日：2018-01-09

申请号：US15375457

申请日：2016-12-12

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L21/768 ,  H01L45/00 ,  H01L23/532

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

公开(公告)号：US09865611B2

公开(公告)日：2018-01-09

申请号：US14867914

申请日：2015-09-28

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L21/311 ,  H01L27/06 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/786

CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0688 ,  H01L29/78642 ,  H01L29/7889

Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

公开(公告)号：US20160260899A1

公开(公告)日：2016-09-08

申请号：US15156105

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

Abstract translation: 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 含金属氧化物的材料形成在第一导电电极上。 蚀刻停止材料沉积在包含金属氧化物的材料上。 导电材料沉积在蚀刻停止材料上。 包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。 这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。 考虑其他实现。

公开(公告)号：US09099431B2

公开(公告)日：2015-08-04

申请号：US14323945

申请日：2014-07-03

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L23/532 ,  H01L49/02 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L28/40 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76882 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract translation: 本文公开了用于从微电子衬底去除导电材料（例如贵金属）的抛光系统和方法。 所述方法的若干实施例包括在基底材料中形成孔，将导电材料设置在基底材料和孔中，并将填充材料设置在导电材料上。 填充材料至少部分地填充孔。 然后抛光衬底材料以去除导电材料和孔的外部的填充材料的至少一部分，在此期间，填充材料在抛光衬底材料期间基本上防止导电材料污染到孔中。