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    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    25.
    发明申请
    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20250069950A1

    公开(公告)日：2025-02-27

    申请号：US18948269

    申请日：2024-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Paolo Tessariol

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

    Abstract: A microelectronic device comprises a stack structure, first dielectric-filled trenches extending vertically through the stack structure, and at least one second dielectric-filled trench intersecting the first dielectric-filled trenches. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The first dielectric-filled trenches divide the stack structure into blocks and extend horizontally in a first direction. At least one second dielectric-filled trench extends horizontally in a second direction orthogonal to the first direction. At least one second dielectric-filled trench has boundaries defined by at least one staircase structure having steps defined by horizontal ends of the tiers in the first direction. Memory devices and electronic systems are also described.

    Memory device including different dielectric structures between blocks
    27.
    发明授权
    Memory device including different dielectric structures between blocks 有权

    公开(公告)号：US12185549B2

    公开(公告)日：2024-12-31

    申请号：US18209204

    申请日：2023-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

    IPC: H01L23/528 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

    Memory array having air gaps
    28.
    发明授权
    Memory array having air gaps 有权

    公开(公告)号：US12156411B2

    公开(公告)日：2024-11-26

    申请号：US17720172

    申请日：2022-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Paolo Tessariol ,  Enrico Varesi ,  Lorenzo Fratin

    IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

    Abstract: Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.

    METHODS TO INCREASE CELL DENSITY USING A LATERAL ETCH
    29.
    发明公开
    METHODS TO INCREASE CELL DENSITY USING A LATERAL ETCH 审中-公开

    公开(公告)号：US20240357815A1

    公开(公告)日：2024-10-24

    申请号：US18637127

    申请日：2024-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Paolo Tessariol ,  Enrico Varesi ,  Emilio Camerlenghi ,  Stephen W. Russell ,  Yoshiaki Fukuzumi

    IPC: H10B43/27

    CPC classification number: H10B43/27

    Abstract: Methods, systems, and devices for methods to increase cell density using a lateral etch are described. A process to manufacture a memory array may include a lateral wet etch to split a pillar into two stacks of memory cells. In some cases, the manufacturing process may include forming a trench in a vertical stack of layers and forming a memory cell pillar which includes an oxide material, a semiconductor channel material, and an insulating material in the trench. Sidewalls of the pillar may be laterally etched to remove portions of the oxide material and the semiconductor material, which may form two stacks of memory cells, each stack in contact with opposing sidewalls of the trench. In some examples, the manufacturing process may include forming one or more supportive piers within the trench, and the pillar of memory cell material may be formed between pairs of piers.

    MERGED CAVITIES FOR CONDUCTOR FORMATION IN A MEMORY DIE
    30.
    发明公开
    MERGED CAVITIES FOR CONDUCTOR FORMATION IN A MEMORY DIE 审中-公开

    公开(公告)号：US20240284672A1

    公开(公告)日：2024-08-22

    申请号：US18443013

    申请日：2024-02-15

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Matthew J. King ,  Indra V. Chary ,  Yoshiaki Fukuzumi ,  Lifang Xu ,  Paolo Tessariol ,  Shuangqiang Luo

    IPC: H10B43/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H10B43/10

    Abstract: Methods, systems, and devices for merged cavities for conductor formation in a memory die are described. An array of cavities may be formed through a stack of material layers of a memory die, and conductors may be formed at least in part by merging some of the cavities of the array. Such cavities may be sized in accordance with a relatively smallest feature that implements a subset of such cavities, and a smallest associated feature may be formed using a first subset of the array of cavities. Conductors may be formed at least in part by merging two or more cavities of a second subset of the array of cavities using a material removal operation to remove portions of the stack of material layers. Such merging may support conductors being formed with a cross-section that is greater than a cross-section of other features formed using such cavities that are not merged.

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