公开(公告)号：US20190147966A1

公开(公告)日：2019-05-16

申请号：US16228733

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US09536618B2

公开(公告)日：2017-01-03

申请号：US14746416

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurielo Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/32 ,  G11C16/16 ,  G11C16/06 ,  G11C16/04 ,  G11C16/08 ,  G11C8/08

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

公开(公告)号：US20160232974A9

公开(公告)日：2016-08-11

申请号：US13957377

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Shigekazu Yamada ,  Tomoharu Tanaka

IPC: G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

公开(公告)号：US20230307056A1

公开(公告)日：2023-09-28

申请号：US18141136

申请日：2023-04-28

Applicant: Micron Technology, Inc.

Inventor： Shigekazu Yamada

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/3459

Abstract: Some embodiments include apparatuses and methods using first and second data lines coupled to respective first and second memory cell strings; an access line shared by first and second memory cells of the first and second memory cell strings, respectively; and a control unit including circuitry to perform operations including charging the first data line to a first voltage during a first time interval of an operation performed on first and second memory cells; holding the second data line at a second voltage during the first time interval; charging the first data line to a third voltage during a second time interval of the operation; charging the second data line to a fourth voltage during the second time interval; and determining, during the second time interval of the operation, whether the first memory cell reaches a first threshold voltage and whether the second memory cell reaches a second threshold voltage.

公开(公告)号：US11670374B2

公开(公告)日：2023-06-06

申请号：US17404204

申请日：2021-08-17

Applicant: Micron Technology, Inc.

Inventor： Shigekazu Yamada

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/3459

Abstract: Some embodiments include apparatuses and methods using first and second data lines coupled to respective first and second memory cell strings; an access line shared by first and second memory cells of the first and second memory cell strings, respectively; and a control unit including circuitry to perform operations including charging the first data line to a first voltage during a first time interval of an operation performed on first and second memory cells; holding the second data line at a second voltage during the first time interval; charging the first data line to a third voltage during a second time interval of the operation; charging the second data line to a fourth voltage during the second time interval; and determining, during the second time interval of the operation, whether the first memory cell reaches a first threshold voltage and whether the second memory cell reaches a second threshold voltage.

公开(公告)号：US20220208274A1

公开(公告)日：2022-06-30

申请号：US17217014

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Shigekazu Yamada

IPC: G11C16/16 ,  G11C16/30

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first control gates for respective first memory cells of the first memory block; a second memory block including second control gates for respective second memory cells of the second memory block; first diffusion regions coupled to the first control gates; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second control gates; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.

公开(公告)号：US20210375375A1

公开(公告)日：2021-12-02

申请号：US17403641

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Michele Piccardi ,  Xiaojiang Guo ,  Shigekazu Yamada

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/04 ,  G11C16/08

Abstract: Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.

公开(公告)号：US10950309B2

公开(公告)日：2021-03-16

申请号：US16036578

申请日：2018-07-16

Applicant: Micron Technology, Inc.

Inventor： Shigekazu Yamada ,  Tomoharu Tanaka

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/16 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

公开(公告)号：US20200049763A1

公开(公告)日：2020-02-13

申请号：US16101563

申请日：2018-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shigekazu Yamada

IPC: G01R31/3177 ,  G01R31/317 ,  G11C29/38

Abstract: A device includes a comparator, a reference signal node electrically coupled to a first input of the comparator, a plurality of test signal nodes, a plurality of first select signal nodes, a first multiplexer coupled between the plurality of test signal nodes and the comparator, a plurality of latches, a plurality of second select signal nodes, and a second multiplexer coupled between an output of the comparator and the plurality of latches. Each first select signal node corresponds to a test signal node. The first multiplexer electrically couples one of the plurality of test signal nodes to a second input of the comparator in response to a corresponding first select signal. Each latch corresponds to a test signal node. Each second select signal node corresponds to a latch. The second multiplexer electrically couples the output of the comparator to an input of one of the plurality of latches in response to a corresponding second select signal.

公开(公告)号：US20190287604A1

公开(公告)日：2019-09-19

申请号：US16430896

申请日：2019-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shigekazu Yamada

IPC: G11C11/4091 ,  G11C16/24 ,  G11C16/14 ,  G11C7/10 ,  G11C7/18 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4094 ,  G11C11/16 ,  G11C7/08

Abstract: Integrated circuit devices include a first node, a second node, a transistor connected between the first node and the second node, a current path between a control gate of the transistor and the second node, and a controller configured to concurrently discharge a voltage level of the first node and a voltage level of the second node, monitor a representation of a voltage difference between the voltage level of the first node and a voltage level of the control gate of the transistor while discharging the voltage level of the first node and discharging the voltage level of the second node, activate the current path if the voltage difference is deemed to be greater than a first value, and deactivate the current path if the voltage difference is deemed to be less than a second value.