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    MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
    21.
    发明公开
    MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20230397401A1

    公开(公告)日：2023-12-07

    申请号：US17830145

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Song Guo ,  Yuan He

    IPC: H01L27/108 ,  G11C5/02

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  G11C5/02

    Abstract: Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.

    SHARED VERTICAL DIGIT LINE FOR SEMICONDUCTOR DEVICES
    24.
    发明申请
    SHARED VERTICAL DIGIT LINE FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220335982A1

    公开(公告)日：2022-10-20

    申请号：US17234052

    申请日：2021-04-19

    Applicant: Micron Technology, Inc.

    Inventor： Yuan He ,  Song Guo

    IPC: G11C5/06 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06

    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and shared vertically oriented digit line. The access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region. Horizontal oriented access lines are coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The shared, vertically oriented digit line is shared between two neighboring horizontal access devices and is coupled to the first source/drain regions of the two neighboring horizontally oriented access devices.

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