公开(公告)号：US20240251552A1

公开(公告)日：2024-07-25

申请号：US18417709

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Mojtaba Asadirad ,  Yiping Wang ,  David H. Wells ,  Matt J. King

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Methods, systems, and devices for NAND staircase landing pads conversion are described. A memory device may include one or more lateral word line contacts that may couple a word line with a conductive pillar that traverses a stack of materials of the memory device. The use of the lateral word line contact may allow for a conductive pillar to be coupled with a target word line without requiring an end of the conductive pillar to be placed directly on the word line. Additionally, the memory architecture described herein may allow for the target word line to be coupled with CMOS circuitry via a first conductive pillar without the use of a second conductive pillar, as the first conductive pillar may traverse the stack of materials and be coupled with the CMOS circuitry. Therefore, total quantity of conductive pillars may be reduced, and the risk of manufacturing errors may be lowered.

公开(公告)号：US11961801B2

公开(公告)日：2024-04-16

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：US20230397422A1

公开(公告)日：2023-12-07

申请号：US17884299

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  David H. Wells ,  Byeung Chul Kim ,  Richard J. Hill ,  Paolo Tessariol

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: Methods, systems, and devices for merged cavities and buried etch stops for three-dimensional memory arrays are described. For example, a row of cavities may be formed using a cavity etching process and material separating cavities of the row may be removed to merge the row of cavities to form a trench. In some cases, a trench may be formed from multiple rows of cavities. Additionally, or alternatively, a trench may be formed from a pattern of cavities that includes different quantities of rows at different locations along the trench. In some examples, etch stopping material portions (e.g., etch stops) may be formed at locations corresponding to cavities prior to the cavity etching process. For example, exposed material surfaces at locations corresponding to cavities or trenches may be oxidized to form etch stops.

公开(公告)号：US20230395511A1

公开(公告)日：2023-12-07

申请号：US17816505

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  David H. Wells

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: Methods, systems, and devices for techniques for concurrently-formed cavities in three-dimensional memory arrays are described. As part of forming a memory die, a plurality of cavities may be formed by a set of one or more material removal operations, and different subsets of the plurality of cavities may be used to form different features of the memory die. In some examples, a sacrificial region may be formed in accordance with one or more material addition or removal operations, and such a sacrificial region may include openings that support the formation of various structures of a memory device. After the formation of such structures, the sacrificial region may be isolated from an active region by merging a subset of the previously-formed plurality of cavities.

公开(公告)号：US20230389314A1

公开(公告)日：2023-11-30

申请号：US17879140

申请日：2022-08-02

Applicant: Micron Technology, Inc

Inventor： Adam Barton ,  David H. Wells ,  Pengyuan Zheng ,  Amritesh Rai

IPC: H01L27/11582 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually directly electrically coupled to individual of the channel-material strings. Digitlines are formed above and are individually directly electrically coupled to a plurality of individual of the conductive vias there-below. The forming of the digitlines comprises forming lower elemental-form tungsten directly against tops of the individual conductive vias. The lower elemental-form tungsten is exposed to oxygen-containing gas or plasma to form WOx, where “x” is greater than 0 and no more than 3.0. The WOx has a maximum thickness greater than 0 and no more than 30 Angstroms in a finished construction. Upper elemental-form tungsten is physical vapor deposited directly against the WOx. Other embodiments, including structure, are disclosed.

公开(公告)号：US11700732B2

公开(公告)日：2023-07-11

申请号：US17146193

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H10B43/50 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

公开(公告)号：US20230065142A1

公开(公告)日：2023-03-02

申请号：US17968651

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11514953B2

公开(公告)日：2022-11-29

申请号：US17243937

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C11/34 ,  G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10971360B2

公开(公告)日：2021-04-06

申请号：US16582109

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Anish A. Khandekar ,  Kunal Shrotri ,  Jie Li

IPC: H01L21/02 ,  H01L27/115 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/786

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

公开(公告)号：US20200020529A1

公开(公告)日：2020-01-16

申请号：US16582109

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Anish A. Khandekar ,  Kunal Shrotri ,  Jie Li

IPC: H01L21/02 ,  H01L27/115

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.