公开(公告)号：US20230209827A1

公开(公告)日：2023-06-29

申请号：US18116946

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H10B43/27 ,  H01L21/311 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/31111 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US20230058170A1

公开(公告)日：2023-02-23

申请号：US17404649

申请日：2021-08-17

Applicant: Micron Technology, Inc

Inventor： Yi Hu

IPC: H01L21/66 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes memory cell strings having respective pillars extending through levels of first conductive materials interleaved with levels of first dielectric materials; conductive structures formed over the memory cell strings and extending through levels of second conductive materials interleaved with levels of second dielectric materials; dielectric structures located in respective trenches over the memory cell strings and dividing the levels of second conductive materials into portions that are electrically separated from each other; and the dielectric structures located such that the distance between two adjacent dielectric structures is different from the distance between two other adjacent dielectric structures.

公开(公告)号：US20220302215A1

公开(公告)日：2022-09-22

申请号：US17804958

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Yi Hu

IPC: H01L27/24 ,  H01L25/065 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/112

Abstract: Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

公开(公告)号：US20220076816A1

公开(公告)日：2022-03-10

申请号：US17012998

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Brooke Spencer ,  Deepti Verma ,  Jennifer F. Huckaby

IPC: G16H40/63 ,  G06N20/00 ,  A61B5/0408

Abstract: Methods, devices, and systems related to a wearable monitor with memory are described. An example device may include an electrode integrated into a multi-chip package (MCP) memory device, the electrode to monitor health data of a wearer of the wearable monitor. The device can include a first processing resource coupled to the MCP memory device, the electrode, or both, to receive the monitored health data. The MCP memory device may store the received health data. The MCP memory device may also be coupled to a wireless communication device. The wireless communication device may transfer the stored health data to a computing device. The computing device may be communicatively coupled to the example device.

公开(公告)号：US20210399012A1

公开(公告)日：2021-12-23

申请号：US17373278

申请日：2021-07-12

Applicant: Micron Technology, Inc

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Twari

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/11519

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US11205654B2

公开(公告)日：2021-12-21

申请号：US16550238

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

公开(公告)号：US20210372785A1

公开(公告)日：2021-12-02

申请号：US16890364

申请日：2020-06-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zahra Hosseinimakarem ,  Jonathan D. Harms ,  Alyssa N. Scarbrough ,  Dmitry Vengertsev ,  Yi Hu

IPC: G01B11/30

Abstract: Embodiments of the disclosure are drawn to projecting light on a surface and analyzing the scattered light to obtain spatial information of the surface and generate a three dimensional model of the surface. The three dimensional model may then be analyzed to calculate one or more surface characteristics, such as roughness. The surface characteristics may then be analyzed to provide a result, such as a diagnosis or a product recommendation. In some examples, a mobile device is used to analyze the surface.

公开(公告)号：US20210249304A1

公开(公告)日：2021-08-12

申请号：US16787321

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Frank Speetjens ,  Darin S. Miller ,  Siva Naga Sandeep Chalamalasetty ,  Dave Pratt ,  Yi Hu ,  Yung-Ta Sung ,  Aaron K. Belsher ,  Allen R. Gibson

IPC: H01L21/768 ,  H01L23/522

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

公开(公告)号：US20200119032A1

公开(公告)日：2020-04-16

申请号：US16160342

申请日：2018-10-15

Applicant: Micron Technology Inc.

Inventor： Yi Hu ,  Jian Li ,  Lifang Xu ,  Xiaosong Zhang

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics.

公开(公告)号：US11700727B2

公开(公告)日：2023-07-11

申请号：US17111275

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Yi Hu ,  Harsh Narendrakumar Jain

IPC: H10B41/27 ,  G11C5/06 ,  G11C5/02 ,  H10B43/27 ,  H10B43/10 ,  H10B43/50 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.