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    ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES
    21.
    发明公开
    ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES 审中-公开

    公开(公告)号：US20240249772A1

    公开(公告)日：2024-07-25

    申请号：US18405049

    申请日：2024-01-05

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/04 ,  G11C5/06 ,  G11C16/30

    CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/30

    Abstract: A semiconductor device can include a substrate of semiconductor material and multiple stacks of memory cells disposed within the substrate. Each of the stacks can include a conductive string that connects memory cells to a bitline where each memory cell is located at an intersection of the conductive string and a wordline. The device can also include capacitor having a cylindrical body disposed between two adjacent stacks of memory cells where the capacitor includes an inner conductive layer and an outer conductive layer at least partially surrounding the inner conductive layer, where the inner conductive layer and the outer conductive layer are separated by a dielectric layer. The device can further include a power supply line conductively connected to an end of the capacitor at a base of the cylindrical body.

    MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM
    22.
    发明公开
    MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240231641A1

    公开(公告)日：2024-07-11

    申请号：US18402306

    申请日：2024-01-02

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Tomer Tzvi Eliash ,  Zhenming Zhou

    IPC: G06F3/06 ,  G06F12/1009

    CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/1009

    Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. The processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. The processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.

    SENSING TIME ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE
    23.
    发明公开
    SENSING TIME ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240203504A1

    公开(公告)日：2024-06-20

    申请号：US18527839

    申请日：2023-12-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/3459

    Abstract: A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A sensing time adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default sensing time is adjusted by the sensing time adjustment value to generate an adjusted sensing time. The program operation on the set of vertically stacked memory cells is performed using the adjusted sensing time.

    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK
    26.
    发明公开
    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK 审中-公开

    公开(公告)号：US20240185924A1

    公开(公告)日：2024-06-06

    申请号：US18524694

    申请日：2023-11-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3459

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells associated with a wordline in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells associated with the wordline in the block using a first pass voltage applied during a program verify phase, wherein the first pass voltage is lower than a default program verify pass voltage.

    ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES
    27.
    发明公开
    ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES 审中-公开

    公开(公告)号：US20240071553A1

    公开(公告)日：2024-02-29

    申请号：US17894528

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

    IPC: G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

    Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

    PROGRAMMING DATA IN MEMORY
    30.
    发明申请
    PROGRAMMING DATA IN MEMORY 有权

    公开(公告)号：US20250130731A1

    公开(公告)日：2025-04-24

    申请号：US18786100

    申请日：2024-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Jun Wan ,  Zhenming Zhou ,  Ying Tai

    IPC: G06F3/06

    Abstract: Programming data in memory is described herein. An example apparatus includes an array of memory cells having a plurality of access lines to which the cells are coupled, and a processing device that performs a program operation on the array, including programming data to be stored in one page of cells of the array to the cells of the array coupled to a first one of the access lines, programming additional data to be stored in that page to the cells of the array coupled to a second one of the access lines adjacent to the first one of the access lines, sensing the data programmed to the cells of the array coupled to the first one of the access lines, and programming data to be stored in two pages of cells of the array to the cells of the array coupled to the first one of the access lines.

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