Abstract:
A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
Abstract:
A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
Abstract:
A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.
Abstract:
A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.
Abstract:
A writing method and a reading method of a phase change memory (PCM) are provided. The PCM has a plurality of memory cells. The writing method comprises the following steps. At least one stress pulse is applied for aging at least one of the memory cells. A starting pulse is applied to all of the memory cells of the PCM for increasing a resistance of each of the memory cells. A detection pulse is applied to all of the memory cells of the PCM for decreasing the resistance of each of the memory cells and detecting the resistance changing speed of each of the memory cells. A set pulse is applied to the aged memory cells. A reset pulse is applied to the non-aged memory cells.
Abstract:
A memory operating method comprises the following steps: a first read voltage is applied to the memory cell to read a first group of data levels of the memory cell; and if the data of the memory cell can not be read with the first read voltage, a second read voltage is applied to the memory cell to read a second group of data levels of the memory cell.
Abstract:
A ReRAM device is provided. The ReRAM device comprises a bottom electrode, a resistance switching layer disposed on the bottom electrode, a top electrode disposed on the resistance switching layer, a metal layer disposed on the top electrode, and a blocking layer covering the metal layer, wherein the blocking layer surrounds the metal layer and the top electrode.
Abstract:
A ReRAM device is provided. The ReRAM device comprises a bottom electrode, a resistance switching layer disposed on the bottom electrode, a top electrode disposed on the resistance switching layer, a metal layer disposed on the top electrode, and a blocking layer covering the metal layer, wherein the blocking layer surrounds the metal layer and the top electrode.
Abstract:
A semiconductor structure includes a memory structure. The memory structure includes a memory element, a first barrier layer and a second barrier layer. The memory element includes titanium oxynitride. The first barrier layer includes at least one of silicon and silicon oxide. The first barrier layer is disposed on the memory element. The second barrier layer includes at least one of titanium and titanium oxide. The second barrier layer is disposed on the first barrier layer.
Abstract:
A method is provided for operating a memory device including an array of memory cells including programmable resistive memory elements. Memory cells in the array are programmed to store data by applying program pulses to the memory cells to establish resistance levels within a number N of specified ranges of resistance, where each of the specified ranges corresponds to a particular data value. A drift recovery process is executed to the memory cells, including applying a recovery pulse having a pulse shape to a set of programmed memory cells, where memory cells in the set have resistance levels within two or more of the specified resistance ranges.