公开(公告)号：US06503846B1

公开(公告)日：2003-01-07

申请号：US09885587

申请日：2001-06-20

申请人： Hiroaki Niimi ,  James J. Chambers ,  Rajesh Khamankar ,  Douglas T. Grider

发明人： Hiroaki Niimi ,  James J. Chambers ,  Rajesh Khamankar ,  Douglas T. Grider

IPC分类号： H01L2131

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.

摘要翻译： 本发明的一个实施例是形成超薄介电层的方法，该方法包括以下步骤：提供具有半导体表面的基板; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体，以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自四种再氧化技术：在H2和N2的混合物中连续退火 （优选小于20％H 2），然后是O 2和N 2（优选小于20％O 2）的混合物;通过尖峰状升温（优选在1000至1150℃下优选小于1秒）在氮气中退火 （优选为N 2 / O 2或N 2 O / H 2）;通过在减压的氨中快速热加热（优选在600至1000℃下5至60秒）进行退火;在氧化剂/氢气混合物（优选N 2 O 1％H 2）在800至1050℃下进行5至60秒。

公开(公告)号：US20120231590A1

公开(公告)日：2012-09-13

申请号：US13474927

申请日：2012-05-18

申请人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

发明人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/28 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/76819 ,  H01L21/823842

摘要： A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.

摘要翻译： 一种设置硅化半导体器件功能的方法及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物层 层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 介电层界面。

公开(公告)号：US07968443B2

公开(公告)日：2011-06-28

申请号：US12344360

申请日：2008-12-26

申请人： Brian K. Kirkpatrick ,  James J. Chambers

发明人： Brian K. Kirkpatrick ,  James J. Chambers

IPC分类号： H01L21/3205

CPC分类号： H01L29/51 ,  H01L21/28247 ,  H01L21/31111 ,  H01L29/495

摘要： A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step.

摘要翻译： 制造CMOS集成电路（IC）的交叉方法包括提供具有顶侧半导体表面，斜面半导体表面和背面半导体表面的半导体晶片，其中斜面半导体表面和背面半导体表面包括硅或锗。 至少在顶侧半导体表面和斜面半导体表面和背面半导体表面的至少一部分上形成包括高k栅极电介质层的金属。 选择性地去除斜面半导体表面和背面半导体表面上的高k介电材料，同时保护顶侧半导体表面上的高k电介质层。 选择性除去包括第一氧化处理，并且包含湿蚀刻的氟化物遵循第一氧化处理。 完成IC的制造，包括在选择性除去步骤之后在高k栅极电介质层上形成至少一个金属栅极层。

公开(公告)号：US20110111586A1

公开(公告)日：2011-05-12

申请号：US13004162

申请日：2011-01-11

申请人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

发明人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/3205

CPC分类号： H01L21/823835 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/76819 ,  H01L21/823842

摘要： A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.

摘要翻译： 一种设置完全硅化半导体器件的功能的方法及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物上的多晶硅层 层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 电介质层界面。

公开(公告)号：US07601578B2

公开(公告)日：2009-10-13

申请号：US11924132

申请日：2007-10-25

申请人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro

发明人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/02318 ,  C23C16/56 ,  H01L21/02323 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/318 ,  H01L29/518 ,  H01L29/78

摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.

摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

公开(公告)号：US07229873B2

公开(公告)日：2007-06-12

申请号：US11200741

申请日：2005-08-10

申请人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

发明人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/04 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

摘要翻译： 本发明提供一种形成双功函数金属栅极微电子器件200的方法。 在一个方面，该方法包括形成nMOS和pMOS堆叠栅极结构315a和315b。 nMOS和pMOS堆叠栅极结构315a和315b各自包括栅极电介质205，位于栅极电介质205上方的第一金属层305和位于第一金属层305上方的牺牲栅极层310。 该方法还包括在nMOS或pMOS堆叠栅极结构中的至少一个中去除牺牲栅极层310，从而形成栅极开口825并修改栅极开口825内的第一金属层305以形成具有所需工作的栅电极 功能。

公开(公告)号：US07119386B2

公开(公告)日：2006-10-10

申请号：US11221103

申请日：2005-09-07

申请人： Mark R. Visokay ,  James J. Chambers

发明人： Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L29/76

CPC分类号： H01L29/7831 ,  H01L29/66484

摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

摘要翻译： 本发明提供一种利用标准半导体衬底（302）制造三栅晶体管段（300）的系统。 衬底具有沿着其上表面以远侧分开的关系形成的多个隔离区域（304），其限定沟道区域（306）。 形式结构（308）设置在隔离区顶部，并且限定通道区域上的通道体区域（310）。 通道体结构（316）设置在通道主体区域内，并被设计成沿着其上暴露表面的周边提供钝角或边缘（318）。 然后去除形式结构，并执行后续处理。

公开(公告)号：US07067434B2

公开(公告)日：2006-06-27

申请号：US10745449

申请日：2003-12-22

申请人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

发明人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

IPC分类号： H01L21/302

CPC分类号： H01L21/28194 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31608 ,  H01L21/3185 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  Y10S438/91 ,  Y10S438/954

摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.

摘要翻译： 本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。 以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

公开(公告)号：US06969644B1

公开(公告)日：2005-11-29

申请号：US10930273

申请日：2004-08-31

申请人： Mark R. Visokay ,  James J. Chambers

发明人： Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7831 ,  H01L29/66484

摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

摘要翻译： 本发明提供一种利用标准半导体衬底（302）制造三栅晶体管段（300）的系统。 衬底具有沿着其上表面以远侧分开的关系形成的多个隔离区域（304），其限定沟道区域（306）。 形式结构（308）设置在隔离区顶部，并且限定通道区域上的通道体区域（310）。 通道体结构（316）设置在通道主体区域内，并被设计成沿着其上暴露表面的周边提供钝角或边缘（318）。 然后去除形式结构，并执行后续处理。

公开(公告)号：US07799668B2

公开(公告)日：2010-09-21

申请号：US11205477

申请日：2005-08-17

申请人： Hiroaki Niimi ,  Luigi Colombo ,  James J. Chambers

发明人： Hiroaki Niimi ,  Luigi Colombo ,  James J. Chambers

IPC分类号： H01L21/3205

CPC分类号： H01L21/823462 ,  H01L21/28185 ,  H01L21/28229 ,  H01L21/31645 ,  H01L21/823857 ,  H01L21/8249 ,  H01L29/517

摘要： The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).

摘要翻译： 本发明提供了形成栅极电介质的方法，其包括在衬底（110）上形成包括金属和至少一种非金属元素的金属源层（210）。 金属源层（210）形成为具有富含金属的组成。 在金属源层（210）之上形成包括金属的电介质层（310）。