公开(公告)号：US07968443B2

公开(公告)日：2011-06-28

申请号：US12344360

申请日：2008-12-26

申请人： Brian K. Kirkpatrick ,  James J. Chambers

发明人： Brian K. Kirkpatrick ,  James J. Chambers

IPC分类号： H01L21/3205

CPC分类号： H01L29/51 ,  H01L21/28247 ,  H01L21/31111 ,  H01L29/495

摘要： A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step.

摘要翻译： 制造CMOS集成电路（IC）的交叉方法包括提供具有顶侧半导体表面，斜面半导体表面和背面半导体表面的半导体晶片，其中斜面半导体表面和背面半导体表面包括硅或锗。 至少在顶侧半导体表面和斜面半导体表面和背面半导体表面的至少一部分上形成包括高k栅极电介质层的金属。 选择性地去除斜面半导体表面和背面半导体表面上的高k介电材料，同时保护顶侧半导体表面上的高k电介质层。 选择性除去包括第一氧化处理，并且包含湿蚀刻的氟化物遵循第一氧化处理。 完成IC的制造，包括在选择性除去步骤之后在高k栅极电介质层上形成至少一个金属栅极层。

公开(公告)号：US07838356B2

公开(公告)日：2010-11-23

申请号：US12347197

申请日：2008-12-31

申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

公开(公告)号：US07732284B1

公开(公告)日：2010-06-08

申请号：US12344421

申请日：2008-12-26

申请人： Brian K. Kirkpatrick ,  Jinhan Choi ,  Deborah J. Riley

发明人： Brian K. Kirkpatrick ,  Jinhan Choi ,  Deborah J. Riley

IPC分类号： H01L21/00

CPC分类号： H01L21/02071 ,  H01L21/31111 ,  H01L29/517 ,  H01L29/78 ,  Y10S438/906

摘要： A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.

摘要翻译： 制造CMOS集成电路（IC）的方法包括提供具有半导体表面的衬底的步骤。 在半导体表面上形成包括金属栅电极在包含高k电介质层的金属上的栅叠层。 使用干蚀刻来图案化栅极堆叠以限定具有金属栅电极的暴露侧壁的图案化栅电极堆叠。 干蚀刻形成后蚀刻残留物，其中一些沉积在基底上。 包括图案化的栅极电极堆叠的衬底暴露于溶液清洁序列，其包括包括第一酸和氟化物的第一清洁步骤，用于去除至少一部分后蚀刻残留物，其中第一清洁步骤具有高选择性以避免 蚀刻金属栅电极的暴露的侧壁。 第一次清洁后的第二次清洁基本上由氟化物组成，其除去半导体表面上残留的高k材料。

公开(公告)号：US07384869B2

公开(公告)日：2008-06-10

申请号：US11100530

申请日：2005-04-07

申请人： Deborah J. Riley ,  Brian M. Trentman ,  Brian K. Kirkpatrick

发明人： Deborah J. Riley ,  Brian M. Trentman ,  Brian K. Kirkpatrick

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/28035 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76224

摘要： A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

摘要翻译： 提供了一种在湿蚀刻和剥离过程中保护暴露的硅免受磷酸侵蚀的方法。 根据该方法的各种实施例，可以在暴露的硅上形成厚的化学氧化物层，以保护暴露部分免受磷酸腐蚀。 该方法可以包括将硅暴露于热臭氧化硫酸和热过氧化硫酸中的至少一种以形成厚的化学氧化物。

公开(公告)号：US06831008B2

公开(公告)日：2004-12-14

申请号：US10261791

申请日：2002-09-30

申请人： Jiong-Ping Lu ,  Glenn J. Tessmer ,  Melissa M. Hewson ,  Donald S. Miles ,  Ralf B. Willecke ,  Andrew J. McKerrow ,  Brian K. Kirkpatrick ,  Clinton L. Montgomery

发明人： Jiong-Ping Lu ,  Glenn J. Tessmer ,  Melissa M. Hewson ,  Donald S. Miles ,  Ralf B. Willecke ,  Andrew J. McKerrow ,  Brian K. Kirkpatrick ,  Clinton L. Montgomery

IPC分类号： H01L2144

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/321 ,  H01L21/3211 ,  H01L21/76834 ,  H01L29/665

摘要： A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel suicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500° C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.

摘要翻译： 描述了在半导体集成电路器件中形成硅化镍和氮化硅结构的工艺。 硅化镍和氮化硅之间的良好粘附性是通过用氮气钝化镍硅化物表面来实现的。 可以通过用等离子体活化的氮物种处理硅化镍表面来进行钝化。 替代的钝化方法是用金属氮化物膜覆盖硅化镍，并将衬底加热至约500℃。另一种替代方法是在硅化镍顶部溅射沉积氮化硅。

公开(公告)号：US06287983B1

公开(公告)日：2001-09-11

申请号：US09213143

申请日：1998-12-18

申请人： Der'E Jan ,  Thomas M. Parrill ,  Brian K. Kirkpatrick

发明人： Der'E Jan ,  Thomas M. Parrill ,  Brian K. Kirkpatrick

IPC分类号： H01L21302

摘要： A nitride wet etch in which liquid TEOS is flowed directly into the hot phosphoric acid bath before wafer etching begins. This preloads the bath chemistry with silicate ions, and thus helps assure very high selectivity to silicon oxides.

公开(公告)号：US08618661B2

公开(公告)日：2013-12-31

申请号：US13251498

申请日：2011-10-03

申请人： Brian K. Kirkpatrick ,  Rajesh Tiwari

发明人： Brian K. Kirkpatrick ,  Rajesh Tiwari

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76879 ,  H01L23/481 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.

摘要翻译： 半导体管芯包括：衬底，其包括被配置为提供电路功能的电路元件的顶面。 模具包括至少一个多层结构，其包括具有第一CTE的第一材料，包括具有第二CTE的金属的第二材料，其中第二CTE高于第一CTE。 热膨胀系数（CTE）渐变层至少包括位于第一材料和第二材料之间的电介质部分，其具有面向第一材料的第一侧面和面向第二材料的第二侧面。 CTE分级层包括横跨其厚度的非恒定组成轮廓，其提供了从第一侧向第二侧增加CTE的分级CTE。 多层结构可以是穿过衬底的厚度的贯穿衬底通孔（TSV）。

公开(公告)号：US08252609B2

公开(公告)日：2012-08-28

申请号：US12757704

申请日：2010-04-09

申请人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

发明人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

IPC分类号： H01L21/26 ,  H01L21/66

CPC分类号： H01L21/26506 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02667 ,  H01L22/12 ,  H01L22/20

摘要： A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

摘要翻译： 一种用于减小具有半导体表面的晶片的曲率的方法。 识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。 晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时与晶体有害的同时，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间， 足以使非晶表面区域再结晶的温度。 由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。

公开(公告)号：US07785957B2

公开(公告)日：2010-08-31

申请号：US12344422

申请日：2008-12-26

申请人： Brian K. Kirkpatrick ,  Jinhan Choi ,  Randall W. Pak

发明人： Brian K. Kirkpatrick ,  Jinhan Choi ,  Randall W. Pak

IPC分类号： H01L21/00

CPC分类号： H01L21/02071 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/823857 ,  Y10S438/906

摘要： A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride. Fabrication of the IC is then completed.

摘要翻译： 一种制造CMOS集成电路（IC）的方法包括提供具有半导体表面的衬底，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 在半导体表面上形成栅极电介质层，然后在栅极介电层上至少形成第一金属包层。 在第一金属包含层上形成多晶硅或非晶硅层以形成中间栅电极堆叠。 在中间栅电极堆叠上形成掩模图案。 使用掩模图案干蚀刻多晶硅或非晶硅层，以在NMOS或PMOS区域上限定图案化的中间栅电极堆叠，其中干蚀刻停止在第一金属层的一部分上。 使用第一后蚀刻清洁来去除掩模图案以剥离掩模图案。 在去除步骤之后使用多步骤溶液清洗顺序，并且包括包括硫酸和氟化物在内的第一次湿清洗，以及在第一次湿清洁之后包括氟化物的第二次湿清洁。 然后完成IC的制造。

公开(公告)号：US07504339B2

公开(公告)日：2009-03-17

申请号：US11142483

申请日：2005-06-01

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

IPC分类号： H01L21/311

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

摘要翻译： 描述半导体材料晶片中的沟槽结构和形成沟槽结构的方法。 沟槽结构形成在半导体晶片上，该半导体晶片具有比半导体材料的其它主要晶面平缓的氧化速度慢的顶表面。 沟槽被蚀刻到半导体晶片中。 沟槽在顶表面附近具有基本垂直的沟槽侧壁，靠近顶表面的垂直沟槽侧壁含有以与顶表面相当的速率氧化的结晶平面。 绝缘层生长在顶表面和沟槽侧壁以及侧壁表面接近顶表面的拐角处，角部处的绝缘层基本上比邻近角部的侧壁厚。 氧化物厚度的差异是由于在拐角处暴露的氧化面更快。 最后，沟槽填充有电介质材料。