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21.发明授权Inhibitory or blocking agents of molecular generating and/or inducing functions 失效分子产生和/或诱导功能的抑制剂或阻断剂公开(公告)号：US07605183B2
公开(公告)日：2009-10-20
申请号：US11889162
申请日：2007-08-09
申请人： Shozo Koyama , Yoshihiro Yamaguchi
发明人： Shozo Koyama , Yoshihiro Yamaguchi
IPC分类号： A61K31/122 , C07C49/607
CPC分类号： C11D3/0084 , A01N35/06 , A61K8/35 , A61K31/12 , A61K31/122 , A61K31/13 , A61K31/40 , A61K31/445 , A61Q5/02 , A61Q19/00 , C08F2/38
摘要： A method for inhibiting or blocking molecular generating and/or inducing functions of molecules using an inhibitory or blocking agent of the formula: wherein R1-6 are as defined herein.
摘要翻译： 使用下式的抑制性或阻断剂抑制或阻断分子产生和/或诱导分子功能的方法：其中R1-6如本文所定义。
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公开(公告)号：US07485921B2
公开(公告)日：2009-02-03
申请号：US11674337
申请日：2007-02-13
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译： 该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。 形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。 在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。 端接层形成为具有大于基底层的结深度的结深度。
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公开(公告)号：US07479678B2
公开(公告)日：2009-01-20
申请号：US11485284
申请日：2006-07-13
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/4236 , H01L29/66727 , H01L29/66734
摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.
摘要翻译： 提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。 第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。 沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。 控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。
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公开(公告)号：USD582951S1
公开(公告)日：2008-12-16
申请号：US29290753
申请日：2008-01-10
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公开(公告)号：US07400007B2
公开(公告)日：2008-07-15
申请号：US11305202
申请日：2005-12-19
IPC分类号： H01L27/108
CPC分类号： H01L29/7813 , H01L29/0696
摘要： A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions are formed. These n+-type source regions and p+-type regions are arranged alternately along a longitudinal direction of the trench gates. The n+-type source regions and the p+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.
摘要翻译： 功率MOSFET包括在n型漂移层上分层形成的n型漂移层和p型基极层。 形成沟槽栅极以穿透p型基极层以到达n型漂移层。 在p型基底层上形成n + +型源区和p + + +型区。 这些n + + +型源极区域和p + + +区域沿沟槽栅极的纵向方向交替布置。 相对于沟槽栅极的纵向方向，n + P +型源极区域和p + H +型区域以倾斜的方式排列。
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公开(公告)号：US20080116512A1
公开(公告)日：2008-05-22
申请号：US11943181
申请日：2007-11-20
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first conductivity type layer and a second conductivity type layer, which are alternately and repeatedly positioned, adjacent to each other, in a column-like fashion on a first conductivity type substrate. The balance of the net charge amount of the impurity between the first conductivity type layer formed under a second conductivity type base layer in the termination region of the semiconductor device and the second conductivity type layer adjacent to the first conductivity type layer is imbalanced in comparison to the balance of the net charge amount of the impurity between the first conductivity type layer in the device-forming region of the semiconductor device and the second conductivity type layer adjacent to the first conductivity type layer.
摘要翻译： 半导体器件包括在第一导电类型衬底上以列状方式彼此相邻地交替地和重复地定位的第一导电类型层和第二导电类型层。 半导体器件的端接区域内的第二导电型基底层下方形成的第一导电型层与第一导电型层相邻的第二导电型层之间的杂质的净电荷量的平衡与第 半导体器件的器件形成区域中的第一导电型层与第一导电型层相邻的第二导电型层之间的杂质的净电荷量的平衡。
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公开(公告)号：US20080099837A1
公开(公告)日：2008-05-01
申请号：US11924175
申请日：2007-10-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译： 该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。 通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。 在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。 第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。
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公开(公告)号：US20080093347A1
公开(公告)日：2008-04-24
申请号：US11907838
申请日：2007-10-18
CPC分类号： H05H1/36
摘要： In a main circuit 11 of the plasma cutter power supply device 6, a plurality of DC power units 14-1, . . . 14-n of low capacity are connected in parallel on their DC output sides, and are connected to a plasma torch 20. Each power unit 14-1, . . . 14-n can operate asynchronously and independently from each other. The power supply control device 6 controls the number of power units to be operated, and the intensity of output electrical current at which each of them is to be operated, according to the cutting conditions (the nature of the material to be cut, its thickness, and the cutting speed) and according to the number of power units which can be operated. If some of the power units are faulty, the power supply control device 6 controls the cutting conditions which can be accepted, according to the number of normal power units.
摘要翻译： 在等离子切割器电源装置6的主电路11中，多个直流电力单元14-1， 。 。 14 -n的低容量在其直流输出侧并联连接，并连接到等离子体焰炬20。 每个电源单元14-1，。 。 。 14 -n可以彼此异步和独立地操作。 电源控制装置6根据切割条件（待切割材料的性质，其厚度等）来控制要操作的功率单元的数量和要各自操作的输出电流的强度 ，切割速度）以及可以操作的动力单元的数量。 如果一些动力单元有故障，则电源控制装置6根据正常功率单元的数量来控制可以接受的切割条件。
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公开(公告)号：US20080066596A1
公开(公告)日：2008-03-20
申请号：US11596677
申请日：2005-05-20
CPC分类号： F16P3/147 , B23K7/002 , B23K7/10 , B23K10/00 , B23K10/006 , B23K26/0876 , B23K26/142 , B23K26/38 , B23K26/702 , B23K37/006 , B23K2101/18 , B23Q15/08 , F16P3/141 , F16P3/144 , G05B2219/43124 , G05B2219/45044 , G05B2219/49074 , Y10T83/05 , Y10T83/081 , Y10T83/8726
摘要： In a thermal cutting machine such as plasma cutting machine or a laser cutting machine, control of the moving speed of a cutting head (24) is improved so as to increase throughput of the cutting machine with increase in cost restricted. Products are cut out one by one from a plate member (14) while a cutting head (24) is moved relative to the plate member (14) on a table (12). In this process, when the cutting head (24) is fast-forwarded without performing cutting to a position at which cutting of each product starts, the speed of movement in the direction (Y-axis direction) along a short side of the table (12) is controlled at a speed higher than that of the movement in the direction (X-axis direction) along a long side of the table. The pattern of a sequence of cutting out the products from the plate member (14) is a meandering pattern in which reciprocation in the Y-axis direction dominates and the movement in the X-direction is one time one way. Exhaust chambers are arranged in the X-axis direction in the table (12), and the exhaust chambers are driven as the cutting head (24) moves in the X-axis direction.
摘要翻译： 在诸如等离子切割机或激光切割机之类的热切割机中，提高了切割头（24）的移动速度的控制，从而在成本受到限制的情况下增加切割机的生产量。 当切割头（24）相对于板构件（14）移动到工作台（12）上时，从板构件（14）逐个切割产品。 在该过程中，当切割头（24）不进行切割到每个产品的切割开始的位置而快进时，沿着桌子的短边方向（Y轴方向）的移动速度 12）以比桌子长边方向（X轴方向）移动速度高的速度进行控制。 从板构件（14）切出产品的顺序的图案是在Y轴方向上的往复运动占主导地位且X方向移动一次的曲折图案。 在台（12）中排列室沿X轴方向排列，当切割头（24）沿X轴方向移动时，排气室被驱动。
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公开(公告)号：US07301178B2
公开(公告)日：2007-11-27
申请号：US11212602
申请日：2005-08-29
申请人： Yoshihiro Yamaguchi , Kenji Oota
发明人： Yoshihiro Yamaguchi , Kenji Oota
IPC分类号： H01L29/74
CPC分类号： H01L29/0661 , H01L24/72 , H01L29/0615 , H01L29/0657 , H01L29/32 , H01L29/74 , H01L2924/0102 , H01L2924/1301 , H01L2924/00
摘要： A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
摘要翻译： AP ++类型的第一扩散层是通过在N +型半导体衬底的正面扩散P型杂质形成的，N型第四扩散层 通过在前侧扩散N型杂质而形成比第一扩散层浅的层，并且P型第二扩散层局部形成为环状，以便通过扩散P而暴露在侧面 型杂质，P型杂质扩散到基板的背面，局部地形成P +型第三扩散层，以从第二层向内分布 扩散层并且不暴露于侧面，并且P型第二扩散层和P + +型第三扩散层形成在两级结构中，因此可以有各种特性 改进。
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