公开(公告)号：US06621860B1

公开(公告)日：2003-09-16

申请号：US09246458

申请日：1999-02-08

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC分类号： H04B346

CPC分类号： G01R29/26

摘要： There is provided an apparatus for and a method of measuring a jitter wherein a clock waveform XC(t) is transformed into an analytic signal using Hilbert transform and a varying term &Dgr;&phgr;(t) of an instantaneous phase of this analytic signal is estimated.

摘要翻译： 提供了一种用于测量抖动的装置和方法，其中使用希尔伯特变换将时钟波形XC（t）变换成分析信号，并且估计该分析信号的瞬时相位的变化项DELTA（t）。

公开(公告)号：US06423558B1

公开(公告)日：2002-07-23

申请号：US09512780

申请日：2000-02-25

申请人： Yasuhiro Maeda ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Yasuhiro Maeda ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： G01R3126

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for fabricating an LSI in which primitive devices such as transistors are formed on a semiconductor substrate and a plurality of interconnect layers are formed thereover to provide sub-circuits of successively larger scale and increasing complexity including sub-circuits which are formed by a connection of the primitive devices and sub-circuits of a larger scale which are formed by a connection of the sub-circuits, under a condition that an intermediate interconnect layer is formed, an exhaustive test, a functional test, a stuck-at fault test, a quiescent power supply current test or the like takes place with respect to the primitive devices or the sub-circuits which are wired together by the intermediate interconnect layer, and subsequently, a wiring connection test takes place after the formation of each subsequent interconnect layer. A fault coverage is improved while a testing cost and a fabricating cost are reduced.

摘要翻译： 在制造LSI的方法中，其中在半导体衬底上形成诸如晶体管的基本器件，并在其上形成多个互连层，以提供连续更大规模的子电路和增加复杂性的子电路，包括由 在形成中间互连层的条件下，通过子电路的连接形成的较大规模的原始器件和子电路的连接，穷举测试，功能测试，卡入故障测试 ，相对于通过中间互连层连接在一起的原始器件或子电路进行静态电源电流测试等，随后在形成每个后续互连层之后进行布线连接测试 。 提高了故障覆盖率，同时降低了测试成本和制造成本。

公开(公告)号：US06291979B1

公开(公告)日：2001-09-18

申请号：US09251096

申请日：1999-02-16

申请人： Mani Soma ,  Takahiro Yamaguchi ,  Masahiro Ishida

发明人： Mani Soma ,  Takahiro Yamaguchi ,  Masahiro Ishida

IPC分类号： G01R2500

CPC分类号： G01R31/2839 ,  G01R25/00 ,  G01R31/3016

摘要： There is provided a method of and an apparatus for detecting delay faults in phase-locked loop circuits. A frequency impulse is applied to a phase-locked loop circuit under test as the reference clock, and a waveform of a signal outputted from the phase-locked loop circuit under test is transformed to an analytic signal to estimate an instantaneous phase of the analytic signal. A linear phase is estimated from the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase. A delay time is measured from this fluctuation term of the instantaneous phase, and further, a delay fault is detected by comparing a time duration during which the phase-locked loop circuit remains in a state of oscillating a certain frequency with a time duration during which a fault-free phase-locked loop circuit remains in a state of oscillating that certain frequency.

摘要翻译： 提供了一种用于检测锁相环电路中的延迟故障的方法和装置。 对被测定的锁相环电路施加频率脉冲作为基准时钟，将从被测锁相环电路输出的信号的波形变换成分析信号，估计分析信号的瞬时相位 。 从估计的瞬时相位估计线性相位，并且从估计的瞬时相位去除估计的线性相位以获得瞬时相位的波动项。 从瞬时相位的波动项测量延迟时间，此外，通过比较锁相环电路保持在某一频率的振荡状态的持续时间与其中的持续时间的时间间隔来检测延迟故障 无故障的锁相环电路保持在某一频率的振荡状态。

公开(公告)号：US07636387B2

公开(公告)日：2009-12-22

申请号：US10776926

申请日：2004-02-11

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma ,  Hirobumi Musha

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma ,  Hirobumi Musha

IPC分类号： H04B3/46

CPC分类号： G01R31/3171 ,  G01R29/26 ,  G01R31/31709 ,  G01R31/31725 ,  G01R31/31922 ,  G01R31/31937 ,  H04L1/205

摘要： A measuring apparatus including a timing jitter estimator which estimates an output timing jitter sequence which indicates the output timing jitter of an output signal based on an output signal output from a DUT in response to an input signal input to the DUT, and a jitter transfer function estimator which estimates a jitter transfer function in the DUT based on the output timing jitter sequence. The jitter transfer function estimator includes an instantaneous phase noise estimator which estimates an instant phase noise of the output signal based on an output signal, and a resampler which generates the output timing jitter sequence by resampling the instantaneous phase noise at predetermined timing.

摘要翻译： 一种测量装置，包括定时抖动估计器，其响应于输入到DUT的输入信号，估计基于从DUT输出的输出信号来输出输出信号的输出定时抖动的输出定时抖动序列，以及抖动传递函数 估计器，其基于输出定时抖动序列来估计DUT中的抖动传递函数。 抖动传递函数估计器包括：基于输出信号估计输出信号的瞬时相位噪声的瞬时相位噪声估计器;以及通过在预定定时重采样瞬时相位噪声来产生输出定时抖动序列的重采样器。

公开(公告)号：US07596173B2

公开(公告)日：2009-09-29

申请号：US11260665

申请日：2005-10-28

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H04B3/46

CPC分类号： H03K5/13 ,  G01R31/31709 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/16

摘要： There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock signals having an almost equal phase difference from each other and a jitter injecting section for injecting jitter into the respective clock signals.

摘要翻译： 提供了一种时钟发生器，用于产生已经注入了抖动的单相时钟，具有用于产生彼此具有几乎相等的相位差的多个时钟信号的多相时钟产生部分，以及用于 将抖动注入相应的时钟信号。

公开(公告)号：US07317309B2

公开(公告)日：2008-01-08

申请号：US10862904

申请日：2004-06-07

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC分类号： G01R23/00 ,  G01R13/00 ,  G10L21/00

CPC分类号： G01R23/16 ,  G01R29/26 ,  G01R31/31709

摘要： A wideband signal analyzing apparatus for analyzing an input signal includes frequency-shifting means for generating a plurality of intermediate frequency signals by shifting a frequency of the input signal as much as respectively different frequency-shifting amounts, so that if a frequency band of the input signal is divided into a plurality of frequency bands, each of the frequency bands can be shifted to a predetermined intermediate band, spectrum measuring means for outputting a complex spectrum of each of the intermediate frequency signals, and spectrum reconstructing means for merging the complex spectra.

摘要翻译： 用于分析输入信号的宽带信号分析装置包括频移装置，用于通过将输入信号的频率分别移动到分别不同的频移量来产生多个中频信号，使得如果输入的频带 信号被分成多个频带，每个频带可以移动到预定的中间频带，用于输出每个中频信号的复谱的频谱测量装置和用于合并复谱的频谱重建装置。

公开(公告)号：US07313496B2

公开(公告)日：2007-12-25

申请号：US11056330

申请日：2005-02-11

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： G01D3/00 ,  G01R27/28

CPC分类号： G01R31/31709 ,  G01R31/2882 ,  G01R31/31716

摘要： A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.

摘要翻译： 用于测试被测设备（DUT）的测试设备包括一个性能板; 用于产生用于测试DUT的测试信号和根据DUT输出的输出信号确定DUT的通过/失败的主框架; 在主框架和执行板之间的引脚电子设备，并在主框架和DUT之间执行发送和接收信号; 确定性抖动注入单元，用于在不通过引脚电子装置的情况下接收输出信号，并将作为所注入的确定性抖动的接收输出信号的环路信号输入到DUT的输入引脚，而不通过引脚电子器件; 以及用于确定DUT的输入引脚是否具有由引脚电子器件输出的测试信号或由确定性抖动注入单元输出的环路信号的开关单元。

公开(公告)号：US20050267696A1

公开(公告)日：2005-12-01

申请号：US10925870

申请日：2004-08-25

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC分类号： G01R29/02 ,  G01R29/027 ,  G01R29/26 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  H04L1/20 ,  G01R15/00

CPC分类号： G01R31/31709 ,  G01R29/02 ,  G01R29/0273 ,  G01R29/26 ,  G01R31/31922 ,  G01R31/31937 ,  H04L1/203 ,  H04L1/205

摘要： A measuring apparatus for measuring reliability against jitter of an electronic device, including: a jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device based on an output signal output from the electronic device according to an input signal input through a transmission line of which the transmission length is shorter than a predetermined length so that it does not generate a deterministic jitter; a jitter tolerance degradation quantity estimator operable to estimate a quantity of degradation of the jitter tolerance which deteriorates by the deterministic jitter caused in the input signal by transmission through the long transmission line when the input signal is input into the electronic device through the transmission line, of which the transmission length is longer than a predetermined length so that it may cause the deterministic jitter; a system jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device and a jitter tolerance of a system including the long transmission line and the electronic device based on quantity of degradation of the jitter tolerance, is provided.

摘要翻译： 一种用于测量电子设备抖动的可靠性的测量装置，包括：抖动容限估计器，用于根据从电子设备输出的输出信号，根据通过传输线输入的输入信号来估计电子设备的抖动容限 其传输长度短于预定长度，使得其不产生确定性抖动; 抖动容忍劣化量估计器，用于当通过传输线路将输入信号输入到电子设备中时，通过传输通过长传输线路来估计在输入信号中产生的确定性抖动而导致的抖动容差劣化的数量， 其传输长度大于预定长度，从而可能导致确定性抖动; 提供了一种用于估计电子设备的抖动容限的系统抖动容限估计器，以及基于抖动容限的劣化量的包括长传输线路和电子设备的系统的抖动容限。

公开(公告)号：US20050129104A1

公开(公告)日：2005-06-16

申请号：US10824763

申请日：2004-04-14

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： G01R29/02 ,  G01R31/28 ,  G01R31/3167 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  H04Q1/20

CPC分类号： G01R31/31709 ,  G01R31/31922 ,  G01R31/31937

摘要： A testing device for testing an electronic device is provided. The testing device includes: a deterministic jitter application unit for applying deterministic jitter to a given input signal without causing an amplitude modulation component and supplying the input signal with the deterministic jitter to the electronic device; a jitter amount controller for controlling the magnitude of the deterministic jitter generated by the deterministic jitter application unit; and a determination unit for determining whether or not the electronic device is defective based on an output signal output from the electronic device in accordance with the input signal.

摘要翻译： 提供了一种用于测试电子设备的测试设备。 测试设备包括：确定性抖动应用单元，用于将确定性抖动应用于给定的输入信号，而不引起幅度调制分量，并向电子设备提供具有确定性抖动的输入信号; 抖动量控制器，用于控制由确定性抖动施加单元产生的确定性抖动的大小; 以及确定单元，用于基于根据输入信号从电子设备输出的输出信号来确定电子设备是否有故障。

公开(公告)号：US06775321B1

公开(公告)日：2004-08-10

申请号：US09703469

申请日：2000-10-31

申请人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Toshifumi Watanabe

发明人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Toshifumi Watanabe

IPC分类号： H04B1700

CPC分类号： G01R29/26

摘要： A signal under measurement is transformed into a complex analytic signal using Hilbert transformation to estimate an instantaneous phase of the signal under measurement from the complex analytic signal. A least mean square line of the instantaneous phase is calculated to obtain a linear instantaneous phase of the signal under measurement, and a zero-crossing timing of the signal under measurement is estimated using an interpolation method. Then a difference between the instantaneous phase and the linear instantaneous phase at the zero-crossing timing is calculated to estimate a timing jitter sequence. A jitter of the signal under measurement is obtained from the jitter sequence.

摘要翻译： 使用希尔伯特变换将测量信号转换成复数分析信号，以从复数分析信号估计测量信号的瞬时相位。 计算瞬时相位的最小均方根以获得测量信号的线性瞬时相位，并且使用内插方法估计测量信号的过零定时。 然后计算在过零时刻的瞬时相位和线性瞬时相位之间的差以估计定时抖动序列。 从抖动序列获得测量信号的抖动。