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21.发明授权Output buffer circuit and differential output buffer circuit, and transmission method 有权输出缓冲电路和差分输出缓冲电路及其传输方式公开(公告)号：US07692445B2
公开(公告)日：2010-04-06
申请号：US11686560
申请日：2007-03-15
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003
CPC分类号： H03K19/018521
摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.
摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。
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公开(公告)号：US20080073504A1
公开(公告)日：2008-03-27
申请号：US11675173
申请日：2007-02-15
IPC分类号： H01J49/00
CPC分类号： H01J49/0036
摘要： In a data acquisition system of ADC system, a log amplifier is provided at the pre-stage of an A/D converter, a signal amplified by the log amplifier having a nonlinear input-output characteristic is A/D-converted, and an adding operation of data is performed while reconverting a voltage value data which is converted to a nonlinear characteristic to data with a linear scale according to a table memory for reverse-log conversion. A known voltage value is inputted into the log amplifier to perform measurement, and calibration of the table memory is performed by storing the voltage value and the voltage value data after A/D-converted.
摘要翻译： 在ADC系统的数据采集系统中，在A / D转换器的前级提供对数放大器，由具有非线性输入输出特性的对数放大器放大的信号进行A / D转换， 执行数据的操作，同时根据用于反向对数转换的表存储器，将转换成非线性特性的电压值数据重新转换成具有线性刻度的数据。 已知的电压值被输入到对数放大器中以进行测量，并且通过在A / D转换后存储电压值和电压值数据来执行表存储器的校准。
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公开(公告)号：US06768953B2
公开(公告)日：2004-07-27
申请号：US10269380
申请日：2002-10-10
IPC分类号： G01R2926
CPC分类号： G01R31/3193
摘要： In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.
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公开(公告)号：US5811877A
公开(公告)日：1998-09-22
申请号：US829144
申请日：1997-03-31
申请人： Ichiro Miyano , Ikuo Kawaguchi , Kunio Matsumoto , Junichi Saeki , Tooru Yoshida , Naoya Kanda , Isamu Yoshida , Michifumi Kawai , Hideo Yamakura , Shigeharu Tsunoda , Ritsuro Orihashi , Masachika Masuda , Sueo Kawai
发明人： Ichiro Miyano , Ikuo Kawaguchi , Kunio Matsumoto , Junichi Saeki , Tooru Yoshida , Naoya Kanda , Isamu Yoshida , Michifumi Kawai , Hideo Yamakura , Shigeharu Tsunoda , Ritsuro Orihashi , Masachika Masuda , Sueo Kawai
IPC分类号： H01L21/50 , H01L21/56 , H01L21/70 , H01L23/28 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10 , H01L23/48 , H01L25/18
CPC分类号： H01L21/565 , H01L23/3107 , H01L23/4951 , H01L23/49568 , H01L25/105 , H01L2224/32014 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/49175 , H01L2224/73215 , H01L2225/1029 , H01L2225/1058 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/3025 , H01L2924/3511
摘要： An ultra-thin resin molded semiconductor device of high reliability with low cost and with easy repair at time of mounting. A plurality of these semiconductor devices are stacked to provide a semiconductor module which has a higher function than semiconductor devices in the same volume, and a card type module utilizing assembled by the stacked semiconductor module is provided. In manufacturing the semiconductor module, an extremely thin lead frame and an LSI chip are directly connected together, and the mirror surface of the LSI chip is exposed by using a low viscosity epoxy resin to have a thin molding. The mirror surface is grinded to have a further thin thickness of the whole structure of the semiconductor device. A part of the lead frame is formed as a reinforcing member, a heat radiation path, a light shielding part for shielding the LSI from harmful light beams, or a positioning base for mounting a substrate. The above ultra-thin resin molded semiconductor devices are interconnected together in a stacked layout to provide a stacked semiconductor module, and to provide a card type device having a higher function.
摘要翻译： 一种超薄树脂模制半导体器件，可靠性高，成本低，安装时易于维修。 多个这些半导体器件被堆叠以提供具有比相同体积的半导体器件更高功能的半导体模块，并且提供利用由堆叠的半导体模块组装的卡型模块。 在制造半导体模块时，将极薄的引线框架和LSI芯片直接连接在一起，并且通过使用低粘度环氧树脂来暴露LSI芯片的镜面以具有薄的成型。 研磨镜面以使半导体器件的整个结构具有更薄的厚度。 引线框架的一部分形成为加强构件，散热路径，用于屏蔽LSI免受有害光束的遮光部分或用于安装基板的定位基座。 上述超薄树脂模制半导体器件以堆叠的布局互连在一起以提供堆叠的半导体模块，并且提供具有更高功能的卡型设备。
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公开(公告)号：US5438259A
公开(公告)日：1995-08-01
申请号：US324924
申请日：1994-10-18
IPC分类号： G01R31/319 , G06F1/10 , H03K5/15 , G04F10/00
CPC分类号： G01R31/3191 , G01R31/31922 , G06F1/10 , H03K5/1504
摘要： In a digital circuitry apparatus in which clock distribution can be performed with high accuracy even in the case where variations in delay time are caused by variations in the apparatus operating condition, programmed input data set to delay circuits are corrected by a circuit portion for measuring the delay time of a phase shifting adjustment delay circuit with respect to variations in delay time caused by variations in the apparatus operating condition, a first arithmetic operation circuit for calculating the rate of variation on the basis of measured values, and a second arithmetic operation circuit for calculating the quantity of variation on the basis of the rate of variation.
摘要翻译： 即使在延迟时间的变化是由设备工作条件的变化引起的情况下也能以高精度执行时钟分配的数字电路装置中，通过电路部分来校正设置到延迟电路的编程输入数据， 延迟时间相对于由设备工作条件的变化引起的延迟时间的变化的延迟时间，第一算术运算电路，用于根据测量值计算变化率;以及第二算术运算电路， 根据变化率计算变化量。
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公开(公告)号：US4755758A
公开(公告)日：1988-07-05
申请号：US804069
申请日：1985-12-03
申请人： Ritsuro Orihashi
发明人： Ritsuro Orihashi
CPC分类号： G01R31/31928 , G01R19/14 , G01R31/31917
摘要： A wave formatter for generating an output waveform used in a logic circuit testing system is disclosd. The wave formatter includes a data generator for outputting in parallel a plurality of data signals having a polarity and a type in response to a control signal for determining the polarity of the data signals and a control data signal for determining the type of the data signals which are received on external input lines of the data generator in synchronism with a test cycle clock. The data generator decodes the control data signals to produce the plurality of data signals in parallel. A shift data supply is provided which receives the plurality of data signals from the data generator and samples the plurality of data signals to output in parallel data signals in response to the test cycle clock. A timing control is provided with external lines for receiving clock input signals and which generate a signal for controlling an operation mode of a shift register on the basis of the clock input signals which are externally supplied to the external lines. A shift register receives the data in parallel with the shift data supply and the signal for controlling an operation mode and outputs the output waveform serially as a function of the signal for controlling an operation mode.
摘要翻译： 公开了一种用于产生在逻辑电路测试系统中使用的输出波形的波形格式器。 波形格式器包括数据发生器，用于响应于用于确定数据信号的极性的控制信号并行输出具有极性和类型的多个数据信号，以及用于确定数据信号的类型的控制数据信号， 与测试周期时钟同步地在数据发生器的外部输入线上接收。 数据发生器解码控制数据信号以并行产生多个数据信号。 提供了一种移位数据电源，其从数据发生器接收多个数据信号，并且响应于测试周期时钟对多个数据信号采样并行数据信号。 定时控制具有用于接收时钟输入信号的外部线路，并且根据外部提供给外部线路的时钟输入信号产生用于控制移位寄存器的操作模式的信号。 移位寄存器与移位数据电源和用于控制操作模式的信号并行地接收数据，并且作为用于控制操作模式的信号的顺序输出输出波形。
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27.发明授权Output buffer circuit and differential output buffer circuit, and transmission method 有权输出缓冲电路和差分输出缓冲电路及其传输方式公开(公告)号：US07969197B2
公开(公告)日：2011-06-28
申请号：US12716796
申请日：2010-03-03
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。
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公开(公告)号：US07474290B2
公开(公告)日：2009-01-06
申请号：US10981715
申请日：2004-11-05
IPC分类号： G09G3/36
CPC分类号： G09G3/006 , G09G3/3688
摘要： A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+ΔV) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.
摘要翻译： 根据本发明的半导体器件具有液晶驱动电路，并且当其灰度电压被测试时，在其中提供的灰度级电压发生器电路中产生的灰度电压（Vx）与参考电压（ 例如，用于测试灰度电压而生成的Vx + DeltaV）和测试结果作为来自半导体器件的外部端子的二值化电压输出。 即使在液晶驱动电路中较高的灰度级或半导体器件的输出端数量增加的情况下，也可以加快灰度电压测试。 因此，可以减少测试所需的时间和成本。
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29.发明申请Output Buffer Circuit and Differential Output Buffer Circuit, and Transmission Method 有权输出缓冲电路和差分输出缓冲电路及传输方式公开(公告)号：US20080265944A1
公开(公告)日：2008-10-30
申请号：US11686560
申请日：2007-03-15
申请人： SATOSHI MURAOKA , Norio Chujo , Ritsuro Orihashi
发明人： SATOSHI MURAOKA , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521
摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.
摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。
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公开(公告)号：US07443373B2
公开(公告)日：2008-10-28
申请号：US11002143
申请日：2004-12-03
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/006 , G09G2310/0289
摘要： A problem, which one of the inventions included in the present application solves, is to provide a semiconductor device that can simultaneously test a plurality of output pins by less channels of a semiconductor test equipment in number than the integrated output pins of the semiconductor device. Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of changing and controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit. When a test is conducted, only one terminal of the gate output outputs a positive voltage VGH or negative voltage VGL and the other terminal is set to a high-impedance state, whereby the plurality of gate outputs are simultaneously tested.
摘要翻译： 包括在本申请中的发明中的一个解决的问题是提供一种半导体器件，其可以通过半导体测试设备的数量少于半导体器件的集成输出引脚的较少通道同时测试多个输出引脚。 代表性的发明之一具有这样的结构，即作为具有驱动液晶显示面板的栅极线的功能的半导体器件的LCD驱动器包括：用于将正和负电压的极性反转的异或电路， 驾驶门线; 能够改变和控制高阻抗状态的用于驱动栅极线的输出电路的三态逆变器电路; 以及用于控制异或电路和三态逆变器电路的测试控制端子TEST中的至少一个。 当进行测试时，仅栅极输出的一个端子输出正电压VGH或负电压VGL，另一个端子被设置为高阻抗状态，从而同时测试多个栅极输出。
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