公开(公告)号：US08736362B2

公开(公告)日：2014-05-27

申请号：US13414218

申请日：2012-03-07

Applicant: Chun-Jen Huang ,  Jiann-Chyi Rau ,  Hsin-Hung Wang

Inventor： Chun-Jen Huang ,  Jiann-Chyi Rau ,  Hsin-Hung Wang

IPC: H03F3/38

CPC classification number: H03F3/38 ,  H03F1/32 ,  H03F3/2173 ,  H03F3/68 ,  H03F2200/351

Abstract: A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.

Abstract translation: 用于放大器的拍频消除电路包括连接在放大器的两个信号处理路径之间的耦合装置，用于补偿信号处理路径之间的输出信号的拍频效果。

公开(公告)号：US20120061840A1

公开(公告)日：2012-03-15

申请号：US13298312

申请日：2011-11-17

Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L23/532

CPC classification number: H01L21/76811

Abstract: A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.

Abstract translation: 公开了一种双镶嵌结构。 双镶嵌结构包括：基底，其上包括镶嵌在基底介电层中的基底电介质层和下部布线层; 基底上的电介质层; 在所述电介质层中的通孔开口，其中所述通孔开口与所述下布线层不对准，从而暴露所述下布线层的一部分和所述基底电介质层的一部分，其中所述通孔开口包括具有凹陷区域的底部; 通过所述通孔开口的内表面的阻挡层，并且覆盖所述露出的下布线层和所述基底介电层，其中仅所述阻挡层填充所述凹陷区域; 以及填充阻挡层上的通孔开口的铜层。

公开(公告)号：US07977244B2

公开(公告)日：2011-07-12

申请号：US11611890

申请日：2006-12-18

Applicant: Yu-Tsung Lai ,  Chun-Jen Huang ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Yu-Tsung Lai ,  Chun-Jen Huang ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.

Abstract translation: 公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并除去。 因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。

公开(公告)号：US07767578B2

公开(公告)日：2010-08-03

申请号：US11621996

申请日：2007-01-11

Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L21/4763

CPC classification number: H01L21/76811

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract translation: 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

公开(公告)号：US20080137427A1

公开(公告)日：2008-06-12

申请号：US11636920

申请日：2006-12-11

Applicant: Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

Inventor： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.

Abstract translation: 本发明的一个实施例涉及一种编程存储器单元的方法。 存储单元处于具有最大初始阈值电压的第一状态。 存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。 在最大初始阈值电压和目标阈值电压之间存在一个提示电压。 存储单元具有漏极区域。 该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度 宽度到第二个脉冲宽度。 第二脉冲宽度小于第一脉冲宽度。

公开(公告)号：US09214859B2

公开(公告)日：2015-12-15

申请号：US13460112

申请日：2012-04-30

Applicant: Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

Inventor： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC: H02M3/07

CPC classification number: H02M3/07

Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

Abstract translation: 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US07692960B2

公开(公告)日：2010-04-06

申请号：US11641992

申请日：2006-12-20

Applicant: Chang-Ting Chen ,  Chun-Jen Huang

Inventor： Chang-Ting Chen ,  Chun-Jen Huang

IPC: G11C7/00

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/3409

Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract translation: 一种用于改善电荷俘获存储单元的擦除效果的方法。 电荷捕获存储单元具有晶体管，其具有耦合到第一位线的第一端子和耦合到第二位线的第二端子。 首先，该方法擦除电荷捕获存储单元。 然后，在电荷捕获存储单元被完全擦除之后，第一位线电连接到第二位线，以使第一位线的电压电平等于第二位线的电压电平，使得第 晶体管的第一端子等于晶体管的第二端子的电压电平。

公开(公告)号：US07474565B2

公开(公告)日：2009-01-06

申请号：US11636920

申请日：2006-12-11

Applicant: Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

Inventor： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.

Abstract translation: 本发明的一个实施例涉及一种编程存储器单元的方法。 存储单元处于具有最大初始阈值电压的第一状态。 存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。 在最大初始阈值电压和目标阈值电压之间存在一个提示电压。 存储单元具有漏极区域。 该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度 宽度到第二个脉冲宽度。 第二脉冲宽度小于第一脉冲宽度。

公开(公告)号：US20080151620A1

公开(公告)日：2008-06-26

申请号：US11641992

申请日：2006-12-20

Applicant: Chang-Ting Chen ,  Chun-Jen Huang

Inventor： Chang-Ting Chen ,  Chun-Jen Huang

IPC: G11C16/14

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/3409

Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract translation: 一种用于改善电荷俘获存储单元的擦除效果的方法。 电荷捕获存储单元具有晶体管，其具有耦合到第一位线的第一端子和耦合到第二位线的第二端子。 首先，该方法擦除电荷捕获存储单元。 然后，在电荷捕获存储单元被完全擦除之后，第一位线电连接到第二位线，以使第一位线的电压电平等于第二位线的电压电平，使得第 晶体管的第一端子等于晶体管的第二端子的电压电平。

公开(公告)号：US20080146036A1

公开(公告)日：2008-06-19

申请号：US11611890

申请日：2006-12-18

Applicant: Yu-Tsung Lai ,  Chun-Jen Huang ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Yu-Tsung Lai ,  Chun-Jen Huang ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L21/3065

CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.

Abstract translation: 公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并将其除去。 因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。