公开(公告)号：US06975558B2

公开(公告)日：2005-12-13

申请号：US10939500

申请日：2004-09-14

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control information and address information, wherein the control information specifies a write operation and the address information specifies a location within a memory array for the write operation. The integrated circuit device may also comprise a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.

Abstract translation: 公开了一种集成电路器件。 在一个特定示例性实施例中，集成电路设备可以包括以多路复用格式接收控制信息和地址信息的第一电路，其中控制信息指定写入操作，并且地址信息指定用于存储器阵列的存储器阵列内的位置 写操作。 集成电路器件还可以包括第二电路，其包括多个输出驱动器以在写入操作期间输出要写入存储器阵列的写入数据，其中写入数据在外部时钟信号的多个时钟周期之后被输出 其中写入数据是响应控制信息输出的，并且其中多个输出驱动器的每个输出驱动器在外部时钟信号的单个时钟周期内输出写数据的两位。

公开(公告)号：US20050033903A1

公开(公告)日：2005-02-10

申请号：US10939500

申请日：2004-09-14

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US06598171B1

公开(公告)日：2003-07-22

申请号：US08829459

申请日：1997-03-28

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C804

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 本发明还包括用于主设备和从设备在总线上进行通信和每个设备中的寄存器的协议，以区分每个设备，并允许总线请求被引导到单个或所有设备。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US06584037B2

公开(公告)日：2003-06-24

申请号：US10102237

申请日：2002-02-04

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C800

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operation of a synchronous memory device. The memory device includes an array of dynamic random access memory cells. The method of operation of the memory device includes receiving an external clock signal, and sampling a first operation code synchronously with respect to the external clock signal, the first operation code specifying a write operation. Additionally, the method of operation of the memory device includes sampling data after a number of clock cycles of the external clock signal transpire. The data is sampled in response to the first operation code.

Abstract translation: 一种同步存储装置的操作方法。 存储器件包括动态随机存取存储器单元阵列。 存储器件的操作方法包括：接收外部时钟信号，并且相对于外部时钟信号同步地对第一操作代码进行采样，第一操作代码指定写入操作。 此外，存储器件的操作方法包括在外部时钟信号的多个时钟周期发生后的采样数据。 响应于第一操作码对数据进行采样。

公开(公告)号：US06452863B2

公开(公告)日：2002-09-17

申请号：US09492982

申请日：2000-01-27

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C800

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling a memory device, wherein the memory device includes a plurality of memory cells. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be input by the memory device in response to a write request. The method further includes issuing a write request to the memory device, wherein in response to the write request the memory device inputs the first amount of data corresponding to the first block size information.

Abstract translation: 一种控制存储器件的方法，其中存储器件包括多个存储器单元。 该方法包括向存储器件提供第一块大小信息，其中第一块大小信息定义响应于写请求由存储器件输入的第一数据量。 该方法还包括向存储器件发出写入请求，其中响应于写入请求，存储器件输入对应于第一块大小信息的第一数据量。

公开(公告)号：US6049846A

公开(公告)日：2000-04-11

申请号：US161090

申请日：1998-09-25

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device includes clock receiver circuitry, clock generation circuitry and input receiver circuitry. The clock receiver circuitry receives an external clock signal from an external bus. The clock generation circuitry is coupled to the clock receiver circuitry, and includes a delay locked loop to generate a first internal clock signal. The input receiver circuitry is coupled to the clock generation circuitry and the external bus to sample information from the external bus in response to the first internal clock signal.

Abstract translation: 一种具有至少一个包括多个存储单元的存储器部分的同步存储器件。 存储器件包括时钟接收器电路，时钟产生电路和输入接收器电路。 时钟接收器电路从外部总线接收外部时钟信号。 时钟发生电路耦合到时钟接收器电路，并且包括延迟锁定环路以产生第一内部时钟信号。 输入接收器电路耦合到时钟产生电路和外部总线，以响应于第一内部时钟信号从外部总线采样信息。

公开(公告)号：US6044426A

公开(公告)日：2000-03-28

申请号：US239522

申请日：1999-01-29

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A memory system having a plurality of memory devices, each having at least one memory array which includes a plurality of memory cells. The memory system comprises a bus, a controller, a first memory device, and a second memory device. The bus includes a plurality of sisal lines coupled to the plurality of memory devices. The bus provides a transaction request including identification information generated by the controller, to the plurality of memory devices. The first and second memory device each include a programmable register, interface circuitry, and comparison circuitry. The interface circuitry of each memory device may store a memory identification value to identify each memory device on the bus. The interface circuitry of each memory device is coupled to the bus to receive a transaction request. The comparison circuitry of each memory device is coupled to the programmable register and the interface circuitry to determine whether the identification information in the transaction request corresponds to the memory identification value wherein when the identification information corresponds to a memory identification value, that memory device responds to the transaction request.

Abstract translation: 一种具有多个存储器件的存储器系统，每个存储器件具有包括多个存储器单元的至少一个存储器阵列。 存储器系统包括总线，控制器，第一存储器件和第二存储器件。 总线包括耦合到多个存储器件的多个剑麻线。 总线提供包括由控制器生成的识别信息的交易请求到多个存储器装置。 第一和第二存储器件各自包括可编程寄存器，接口电路和比较电路。 每个存储器件的接口电路可以存储存储器标识值以识别总线上的每个存储器件。 每个存储器件的接口电路被耦合到总线以接收事务请求。 每个存储器件的比较电路耦合到可编程寄存器和接口电路，以确定事务请求中的识别信息是否对应于存储器标识值，其中当识别信息对应于存储器标识值时，该存储器件响应于 交易请求。

公开(公告)号：US6032214A

公开(公告)日：2000-02-29

申请号：US252998

申请日：1999-02-19

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The present invention is directed to a method of operating a memory device wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to a first external clock signal and a second external clock signal. In one preferred embodiment, the method may further include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the first and second external clock transpire. The number of clock cycles may be a whole number or a fraction.

Abstract translation: 本发明涉及一种操作存储器件的方法，其中存储器件包括多个存储器单元。 该方法包括向存储器设备提供第一块大小信息，其中响应于读请求，第一块大小信息定义要输出到总线上的第一数据量。 该方法还包括向存储器件发出第一读取请求，其中响应于第一读取请求，存储器件相对于第一外部时钟同步地将与第一块大小信息相对应的第一数据量数据输出到总线上 信号和第二个外部时钟信号。 在一个优选实施例中，该方法可以进一步包括提供代表在数据由存储器件输出到总线上之前要发出的第一和第二外部时钟的数量的时钟周期的代码。 存储器件将代码存储在存储器件上的可编程寄存器中。 在该优选实施例中，在第一外部时钟和第二外部时钟的时钟周期数出现之后输出对应于第一块大小信息的第一数据量。 时钟周期的数量可以是整数或分数。

公开(公告)号：US5995443A

公开(公告)日：1999-11-30

申请号：US262114

申请日：1999-03-04

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/006 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

公开(公告)号：US5915105A

公开(公告)日：1999-06-22

申请号：US979127

申请日：1997-11-26

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.