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公开(公告)号：US20120326333A1
公开(公告)日：2012-12-27
申请号：US13607680
申请日：2012-09-08
IPC分类号： H01L25/00
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
摘要翻译： 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。
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22.发明授权System and computer program product for dynamically managing power in microprocessor chips according to present processing demands 有权系统和计算机程序产品，用于根据当前的处理需求动态管理微处理器芯片的电源公开(公告)号：US07647519B2
公开(公告)日：2010-01-12
申请号：US12131507
申请日：2008-06-02
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译： 公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。 选择执行一个进程。 然后识别执行该过程所需的硬件元素。 微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。
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公开(公告)号：US07484043B2
公开(公告)日：2009-01-27
申请号：US10603251
申请日：2003-06-25
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0824
摘要： A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a a hypervisor.
摘要翻译： 多处理器计算机系统具有多个处理节点，其使用处理器状态信息来确定系统中哪些相干高速缓存需要检查由单个发起处理器的存储请求产生的一致性事务。 计算机的节点具有动态一致性边界，使得硬件在任何特定时间点仅使用大型系统中的单个工作负载的总处理器的子集，并且可以在主管软件或固件扩展和收缩时优化高速缓存一致性 用于运行任何单个工作负载的处理器数量。 节点的多个实例可以与第二级控制器连接，以创建大型多处理器系统。 节点控制器使用模式位来确定哪些处理器必须接收节点控制器接收的任何给定事务。 第二级控制器使用模式位来确定哪些节点必须接收由第二级控制器接收的任何给定事务。 逻辑分区映射到允许的物理处理器。 选择包含系统中总处理器和高速缓存的子集的高速缓存相干区域用于物理接近。 可以使用管理程序为每个分区定义不同的高速缓存一致性区域。
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24.发明授权Method for dynamically managing power in microprocessor chips according to present processing demands 有权根据当前处理需求动态管理微处理器芯片功率的方法公开(公告)号：US07401240B2
公开(公告)日：2008-07-15
申请号：US10860407
申请日：2004-06-03
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译： 公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。 选择执行一个进程。 然后识别执行该过程所需的硬件元素。 微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。
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25.发明申请APPARATUS FOR MODELING QUEUEING SYSTEMS WITH HIGHLY VARIABLE TRAFFIC ARRIVAL RATES 失效用于建立具有高可变交通抵达率的排队系统的装置公开(公告)号：US20080151923A1
公开(公告)日：2008-06-26
申请号：US12036043
申请日：2008-02-22
IPC分类号： H04L12/28
CPC分类号： H04L41/145 , H04L43/0852 , H04L49/90
摘要： An apparatus are provided for modeling queuing systems with highly variable traffic arrival rates. The apparatus includes a means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.
摘要翻译： 提供了一种用于建模具有高度可变的交通量到达率的排队系统的装置。 该装置包括将值与简单和直观的高度可变到达速率的模式相关联的装置，以及用于在以突发的到达活动为特征的系统中精确地建模排队延迟的装置。 基于随机到达速率首先将加权因子应用于排队延迟，以及基于突发可变到达速率的排队延迟的不同加权因子，排队延迟由排队延迟的和确定。 权重因素是服务器利用率的变体。 该模型有助于规范服务器特性和配置以满足响应时间度量。
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公开(公告)号：US20080147988A1
公开(公告)日：2008-06-19
申请号：US12037172
申请日：2008-02-26
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0824
摘要： A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a hypervisor.
摘要翻译： 多处理器计算机系统具有多个处理节点，其使用处理器状态信息来确定系统中哪些相干高速缓存需要检查由单个发起处理器的存储请求产生的一致性事务。 计算机的节点具有动态一致性边界，使得硬件在任何特定时间点仅使用大型系统中的单个工作负载的总处理器的子集，并且可以在主管软件或固件扩展和收缩时优化高速缓存一致性 用于运行任何单个工作负载的处理器数量。 节点的多个实例可以与第二级控制器连接，以创建大型多处理器系统。 节点控制器使用模式位来确定哪些处理器必须接收节点控制器接收的任何给定事务。 第二级控制器使用模式位来确定哪些节点必须接收由第二级控制器接收的任何给定事务。 逻辑分区映射到允许的物理处理器。 选择包含系统中总处理器和高速缓存的子集的高速缓存相干区域用于物理接近。 可以使用管理程序为每个分区定义不同的高速缓存一致性区域。
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27.发明授权Apparatus and method for modeling queueing systems with highly variable traffic arrival rates 失效用于建模具有高可变流量到达率的排队系统的装置和方法公开(公告)号：US07376083B2
公开(公告)日：2008-05-20
申请号：US10731862
申请日：2003-12-09
IPC分类号： H04L12/56
CPC分类号： H04L41/145 , H04L43/0852 , H04L49/90
摘要： A method are provided for modeling queuing systems with highly variable traffic arrival rates. The method includes a means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.
摘要翻译： 提供了一种用于建模具有高可变流量到达率的排队系统的方法。 该方法包括将值与简单和直观的高度可变到达速率的模式相关联的手段，以及用于在以突发的到达活动为特征的系统中精确地建模排队延迟的手段。 基于随机到达速率首先将加权因子应用于排队延迟，以及基于突发可变到达速率的排队延迟的不同加权因子，排队延迟由排队延迟的和确定。 加权因子是服务器利用率的变体。 该模型有助于规范服务器特性和配置以满足响应时间度量。
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28.发明申请公开(公告)号：US20080059769A1
公开(公告)日：2008-03-06
申请号：US11468547
申请日：2006-08-30
IPC分类号： G06F9/40
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.
摘要翻译： 支持多指令集架构的多核处理器为需要多个支持多指令集体系结构（ISAs）的虚拟机环境提供功率高效且灵活的平台。 处理器包括具有不同的本地ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 多个核心可以共享公共的第一级高速缓存并且被互斥地选择用于操作，或者可以提供多个一级缓存，一个与每个核心和根据需要运行的核心相关联，包括同时执行不同的ISA。 虚拟机管理程序控制核心的操作并定位核心，并且如果需要，当接收到具有指定的ISA的虚拟机的实例化请求时，它可以启用它。
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公开(公告)号：US09170948B2
公开(公告)日：2015-10-27
申请号：US13726146
申请日：2012-12-23
CPC分类号： G06F12/0828 , G11C5/025 , G11C8/12 , G11C29/12 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/06541 , H01L2225/06565 , H01L2924/1461 , H01L2924/15311 , Y02D10/13 , H01L2924/00
摘要： A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices.
摘要翻译： 堆叠堆叠的存储器件实现集成的一致性管理器以卸载处理系统的设备的高速缓存一致性协议操作。 芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一组一个或多个逻辑管芯。 一个或多个逻辑模块实现提供存储器接口和一致性管理器的硬件逻辑。 存储器接口操作以响应来自一致性管理器和一个或多个外部设备的存储器访问请求来执行存储器访问。 相关性管理器包括对存储在堆叠存储器管芯上的共享数据执行一致性操作的逻辑。 由于逻辑管芯和存储器管芯的集成，一致性管理器可以访问存储在存储器管芯中的共享数据，并且与外部器件相比具有更高带宽和更低的延迟和功耗的相关一致性操作。
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公开(公告)号：US08686559B2
公开(公告)日：2014-04-01
申请号：US13607680
申请日：2012-09-08
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
摘要翻译： 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。
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