公开(公告)号：US20120187420A1

公开(公告)日：2012-07-26

申请号：US13427963

申请日：2012-03-23

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

IPC分类号： H01L29/16 ,  H01L29/78

CPC分类号： H01L23/485 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76283 ,  H01L21/76877 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有第一栅极结构的p型半导体器件，该第一栅极结构包括存在于半导体衬底上的栅极电介质，p型功函数金属层，由钛构成的金属层和 铝和由铝构成的金属填充物。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。 层间电介质存在于半导体衬底上。 层间电介质包括到p型和n型半导体器件的源区和漏区的互连。 互连由钛和铝构成的金属层和由铝组成的金属填充物构成。 本公开还提供了形成上述结构的方法。

公开(公告)号：US20120181630A1

公开(公告)日：2012-07-19

申请号：US13006656

申请日：2011-01-14

申请人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

发明人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

公开(公告)号：US08105892B2

公开(公告)日：2012-01-31

申请号：US12542768

申请日：2009-08-18

申请人： Byeong Y. Kim ,  Michael P. Chudzik

发明人： Byeong Y. Kim ,  Michael P. Chudzik

IPC分类号： H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/7833

摘要： A method is provided that includes providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region and forming a thin gate oxide pFET within the thin gate oxide pFET device region and a thick gate oxide pFET within the thick gate oxide pFET device region. The thin gate oxide pFET that is formed includes a layer of SiGe on an upper surface of the thin gate oxide pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer. The thick gate oxide pFET that is formed includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.

摘要翻译： 提供了一种方法，其包括提供至少包括薄栅极氧化物pFET器件区域和厚栅极氧化物pFET器件区域的半导体衬底，并在薄栅极氧化物pFET器件区域内形成薄栅极氧化物pFET，并在其内形成厚栅极氧化物pFET 厚栅氧化物pFET器件区域。 所形成的薄栅氧化物pFET包括在薄栅极氧化物pFET器件区域的上表面上的SiGe层，位于SiGe层的上表面上的高k栅极电介质，pFET阈值电压调节层，位于 高k栅极电介质的上表面，以及pFET阈值电压调节层顶部的栅极导体材料。 形成的厚栅极氧化物pFET包括位于厚栅极氧化物pFET器件区域的上表面上的热氧化物，位于热氧化物的上表面上的硅层和位于硅层顶部的栅极导体材料。

公开(公告)号：US08021939B2

公开(公告)日：2011-09-20

申请号：US11954775

申请日：2007-12-12

申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

IPC分类号： H01L21/8238

CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

公开(公告)号：US20100244206A1

公开(公告)日：2010-09-30

申请号：US12414794

申请日：2009-03-31

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  Rashmi Jha ,  Young-Hee Kim ,  Siddarth A. Krishnan ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  Rashmi Jha ,  Young-Hee Kim ,  Siddarth A. Krishnan ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L23/00 ,  H01L21/314

CPC分类号： H01L21/28202 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

摘要翻译： 形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。 高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

公开(公告)号：US20100187610A1

公开(公告)日：2010-07-29

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

公开(公告)号：US20100181630A1

公开(公告)日：2010-07-22

申请号：US12355953

申请日：2009-01-19

申请人： Huiming Bu ,  Michael P. Chudzik ,  Ricardo A. Donaton ,  Naim Moumen ,  Hongwen Yan

发明人： Huiming Bu ,  Michael P. Chudzik ,  Ricardo A. Donaton ,  Naim Moumen ,  Hongwen Yan

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.

摘要翻译： 通过在栅极堆叠上施加衬垫，在栅堆叠之间施加填充材料，将填充材料平坦化，将填充材料平坦化，形成低电阻接触到金属栅极或包括高集成度密度集成电路中的高K栅极电介质的晶体管 支持高分辨率光刻，相互选择性地蚀刻填充材料和衬垫以形成通孔并用金属，金属合金或导电金属化合物如氮化钛填充通孔。

公开(公告)号：US20090294920A1

公开(公告)日：2009-12-03

申请号：US12132146

申请日：2008-06-03

申请人： Michael P. Chudzik ,  Rashmi Jha ,  Naim Moumen ,  Keith Kwong Hon Wong ,  Ying H. Tsang

发明人： Michael P. Chudzik ,  Rashmi Jha ,  Naim Moumen ,  Keith Kwong Hon Wong ,  Ying H. Tsang

IPC分类号： H01L23/58 ,  H01L21/311

CPC分类号： H01L21/31133 ,  H01L21/31127 ,  H01L21/31138

摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.

摘要翻译： 公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。 所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。 去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。 去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。 或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。 通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

公开(公告)号：US20090280631A1

公开(公告)日：2009-11-12

申请号：US12117769

申请日：2008-05-09

申请人： Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

发明人： Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.

摘要翻译： 本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部上形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属顶上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。

公开(公告)号：US07569466B2

公开(公告)日：2009-08-04

申请号：US11303715

申请日：2005-12-16

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842

摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.

摘要翻译： 包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极 提供电极。 本发明还提供一种制造这种半导体结构的方法。