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公开(公告)号：US20090280631A1
公开(公告)日：2009-11-12
申请号：US12117769
申请日：2008-05-09
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/82345 , H01L21/823462 , H01L29/4966 , H01L29/517
摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.
摘要翻译： 本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部上形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属顶上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。
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公开(公告)号：US07781321B2
公开(公告)日：2010-08-24
申请号：US12117769
申请日：2008-05-09
IPC分类号： H01L21/44
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/82345 , H01L21/823462 , H01L29/4966 , H01L29/517
摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.
摘要翻译： 本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属的顶部上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。
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公开(公告)号：US08507992B2
公开(公告)日：2013-08-13
申请号：US13048170
申请日：2011-03-15
申请人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
发明人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.
摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。
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4.发明申请HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION 有权具有隔离区域的最小重叠的高K电介质和金属栅极堆叠公开(公告)号：US20110227171A1
公开(公告)日：2011-09-22
申请号：US13150378
申请日：2011-06-01
IPC分类号： H01L29/51
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。
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5.发明申请METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS 审中-公开具有低电荷捕获的金属栅极和用于高k栅介质堆叠的增强的电介质可靠性特性公开(公告)号：US20100044805A1
公开(公告)日：2010-02-25
申请号：US12609555
申请日：2009-10-30
申请人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
发明人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L21/28518 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.
摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。
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6.发明申请HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION AND RELATED METHODS 失效具有隔离区域的最小重叠的高K电介质和金属栅极堆栈及相关方法公开(公告)号：US20090152650A1
公开(公告)日：2009-06-18
申请号：US11954775
申请日：2007-12-12
IPC分类号： H01L29/49 , H01L21/283
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。
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7.发明授权High-K dielectric and metal gate stack with minimal overlap with isolation region 有权高K电介质和金属栅极堆叠与隔离区域重叠公开(公告)号：US08232606B2
公开(公告)日：2012-07-31
申请号：US13150378
申请日：2011-06-01
IPC分类号： H01L29/76
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。
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8.发明授权High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods 失效高k介质和金属栅极堆叠与隔离区域和相关方法的重叠最小公开(公告)号：US08021939B2
公开(公告)日：2011-09-20
申请号：US11954775
申请日：2007-12-12
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。
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9.发明申请METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS 审中-公开用于高K金属栅极晶体管的阈值电压控制和驱动电流改进的方法和结构公开(公告)号：US20100244206A1
公开(公告)日：2010-09-30
申请号：US12414794
申请日：2009-03-31
申请人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L23/00 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
摘要翻译： 形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。 高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。
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10.发明申请STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME 审中-公开具有改进的通道移动性的CMOS器件的应变金属栅结构及其形成方法公开(公告)号：US20080203485A1
公开(公告)日：2008-08-28
申请号：US11680108
申请日：2007-02-28
申请人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
发明人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/78 , H01L29/7845
摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
摘要翻译： 用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。 第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。
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