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    Thermal dual gate oxide device integration
    1.
    发明授权
    Thermal dual gate oxide device integration 有权
    热双栅氧化器器件集成

    公开(公告)号：US08105892B2

    公开(公告)日：2012-01-31

    申请号：US12542768

    申请日：2009-08-18

    申请人： Byeong Y. Kim ,  Michael P. Chudzik

    发明人： Byeong Y. Kim ,  Michael P. Chudzik

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0922 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/7833

    摘要： A method is provided that includes providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region and forming a thin gate oxide pFET within the thin gate oxide pFET device region and a thick gate oxide pFET within the thick gate oxide pFET device region. The thin gate oxide pFET that is formed includes a layer of SiGe on an upper surface of the thin gate oxide pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer. The thick gate oxide pFET that is formed includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.

    摘要翻译： 提供了一种方法，其包括提供至少包括薄栅极氧化物pFET器件区域和厚栅极氧化物pFET器件区域的半导体衬底，并在薄栅极氧化物pFET器件区域内形成薄栅极氧化物pFET，并在其内形成厚栅极氧化物pFET 厚栅氧化物pFET器件区域。 所形成的薄栅氧化物pFET包括在薄栅极氧化物pFET器件区域的上表面上的SiGe层，位于SiGe层的上表面上的高k栅极电介质，pFET阈值电压调节层，位于 高k栅极电介质的上表面，以及pFET阈值电压调节层顶部的栅极导体材料。 形成的厚栅极氧化物pFET包括位于厚栅极氧化物pFET器件区域的上表面上的热氧化物，位于热氧化物的上表面上的硅层和位于硅层顶部的栅极导体材料。

    THERMAL DUAL GATE OXIDE DEVICE INTEGRATION
    2.
    发明申请
    THERMAL DUAL GATE OXIDE DEVICE INTEGRATION 有权
    热双通道氧化物装置集成

    公开(公告)号：US20110042751A1

    公开(公告)日：2011-02-24

    申请号：US12542768

    申请日：2009-08-18

    申请人： Byeong Y. Kim ,  Michael P. Chudzik

    发明人： Byeong Y. Kim ,  Michael P. Chudzik

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L27/0922 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/7833

    摘要： A method is provided that includes providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region and forming a thin gate oxide pFET within the thin gate oxide pFET device region and a thick gate oxide pFET within the thick gate oxide pFET device region. The thin gate oxide pFET that is formed includes a layer of SiGe on an upper surface of the thin gate oxide pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer. The thick gate oxide pFET that is formed includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.

    摘要翻译： 提供了一种方法，其包括提供至少包括薄栅极氧化物pFET器件区域和厚栅极氧化物pFET器件区域的半导体衬底，并在薄栅极氧化物pFET器件区域内形成薄栅极氧化物pFET，并在其内形成厚栅极氧化物pFET 厚栅氧化物pFET器件区域。 所形成的薄栅氧化物pFET包括在薄栅极氧化物pFET器件区域的上表面上的SiGe层，位于SiGe层的上表面上的高k栅极电介质，pFET阈值电压调节层，位于 高k栅极电介质的上表面，以及pFET阈值电压调节层顶部的栅极导体材料。 形成的厚栅极氧化物pFET包括位于厚栅极氧化物pFET器件区域的上表面上的热氧化物，位于热氧化物的上表面上的硅层和位于硅层顶部的栅极导体材料。

    High-K/metal gate stack using capping layer methods, IC and related transistors
    3.
    发明授权
    High-K/metal gate stack using capping layer methods, IC and related transistors 有权
    高K /金属栅极堆叠采用封盖层法，IC及相关晶体管

    公开(公告)号：US09236314B2

    公开(公告)日：2016-01-12

    申请号：US13433659

    申请日：2012-03-29

    申请人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    发明人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L29/51

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

    摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

    摘要翻译： 公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。 在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

    Techniques for the Fabrication of Thick Gate Dielectric
    5.
    发明申请
    Techniques for the Fabrication of Thick Gate Dielectric 失效
    厚栅电介质制造技术

    公开(公告)号：US20130292778A1

    公开(公告)日：2013-11-07

    申请号：US13464966

    申请日：2012-05-05

    申请人： Eduard Albert Cartier ,  Michael P. Chudzik ,  Andreas Kerber ,  Siddarth Krishnan ,  Naim Moumen

    发明人： Eduard Albert Cartier ,  Michael P. Chudzik ,  Andreas Kerber ,  Siddarth Krishnan ,  Naim Moumen

    IPC分类号： H01L27/092 ,  H01L21/76

    CPC分类号： H01L21/823857 ,  H01L21/76224

    摘要： A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.

    摘要翻译： 一种制造CMOS器件的方法包括以下步骤。 提供晶片。 STI用于在晶片中形成至少一个有效区域。 氧化硅层沉积在覆盖有源区的晶片上。 第一高k材料沉积在氧化硅层上。 选择性地去除氧化硅层和第一高k材料的部分，使得氧化硅层和第一高k材料保留在有源区的一个或多个第一区上，并从一个或多个第二个 活跃区域。 在有源区域的一个或多个第一区域上并且在有源区域的一个或多个第二区域中的晶片的表面上沉积第二高k材料到第一高k材料上。 还提供了CMOS器件。

    Replacement gate devices with barrier metal for simultaneous processing
    8.
    发明授权
    Replacement gate devices with barrier metal for simultaneous processing 失效
    具有隔离金属的替换门装置用于同时处理

    公开(公告)号：US08420473B2

    公开(公告)日：2013-04-16

    申请号：US12960586

    申请日：2010-12-06

    申请人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

    发明人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

    IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7848

    摘要： A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

    摘要翻译： 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。

    SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
    9.
    发明申请
    SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY 有权
    用于金属高K介电金属绝缘体金属（MIM）嵌入式动态随机存取存储器的自对准底板

    公开(公告)号：US20130062677A1

    公开(公告)日：2013-03-14

    申请号：US13228767

    申请日：2011-09-09

    申请人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

    发明人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

    IPC分类号： H01L21/20 ,  H01L27/06

    CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/945

    摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

    摘要翻译： 提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。 在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。 电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层 金属电极。 存储器件还包括与电容器电连通的传输晶体管。

    Method of providing threshold voltage adjustment through gate dielectric stack modification
    10.
    发明授权
    Method of providing threshold voltage adjustment through gate dielectric stack modification 有权
    通过栅介质叠层修改提供阈值电压调整的方法

    公开(公告)号：US08354309B2

    公开(公告)日：2013-01-15

    申请号：US13347014

    申请日：2012-01-10

    申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

    发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

    摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

    摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。