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42 条记录 (耗时 0.03 秒)

    Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor
    21.
    发明授权
    Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor 有权
    制造双晶硅，异质结基极型和相应晶体管的双极晶体管的方法

    公开(公告)号：US06744080B2

    公开(公告)日：2004-06-01

    申请号：US10097651

    申请日：2002-03-13

    申请人： Alain Chantre ,  Helene Baudry ,  Didier Dutartre

    发明人： Alain Chantre ,  Helene Baudry ,  Didier Dutartre

    IPC分类号： H01L2973

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

    摘要翻译： 晶体管和双晶硅异质结基极型双极晶体管的制造方法，其中具有SiGe异质结的半导体层通过非选择性外延在衬底的有源区和围绕有源区的绝缘区形成。 在有源区域的一部分上方的半导体层上形成至少一个阻挡层。 在半导体层和停止层的一部分上形成多晶硅层和上绝缘层，留下发射器窗口。 发射极区域通过在发射极窗中外延形成，部分地搁置在上绝缘层上并与半导体层接触。

    PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS
    24.
    发明申请
    PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS 审中-公开
    形成外延层的方法，特别是完全放电的晶体管的源和漏区

    公开(公告)号：US20120252174A1

    公开(公告)日：2012-10-04

    申请号：US13434923

    申请日：2012-03-30

    申请人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

    发明人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

    IPC分类号： H01L21/336 ,  H01L21/20

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7848

    摘要： A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.

    摘要翻译： 在单晶半导体结构和多晶半导体结构上外延生长半导体材料层。 然后蚀刻外延层，以便在单晶结构上保留所述材料的非零厚度，并在多晶结构上保持零厚度。 在每个重复中，使用相同的材​​料或不同的材料重复生长和蚀刻的过程，直到所述单晶结构上的一叠外延层已经达到期望的厚度。 单晶结构优选为晶体管的源/漏区，多晶结构优选为该晶体管的栅极。

    Method for integrating silicon-on-nothing devices with standard CMOS devices
    25.
    发明授权
    Method for integrating silicon-on-nothing devices with standard CMOS devices 有权
    将无硅器件与标准CMOS器件集成的方法

    公开(公告)号：US07906381B2

    公开(公告)日：2011-03-15

    申请号：US12167282

    申请日：2008-07-03

    申请人： Nicolas Loubet ,  Didier Dutartre ,  Stéphane Monfray

    发明人： Nicolas Loubet ,  Didier Dutartre ,  Stéphane Monfray

    IPC分类号： H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207

    摘要： A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.

    摘要翻译： 提供了一种用于在单个衬底中制造第一和第二类型的晶体管的方法。 衬底的第一和第二活性区由横向隔离沟槽区限定，并且去除第二活性区的一部分，使得第二活性区位于第一活性区以下。 第一和第二层半导体材料形成在第二有源区上，使得第二层基本上处于与第一活性区相同的平面。 在第一活性区和第二层产生绝缘栅。 选择性地去除至少一个隔离沟槽区域，并且选择性地去除第一层，以便在第二层下形成隧道。 隧道填充有电介质材料以使第二层与衬底的第二活性区绝缘。 还提供了这种集成电路。

    Forming of a single-crystal semiconductor layer portion separated from a substrate
    27.
    发明授权
    Forming of a single-crystal semiconductor layer portion separated from a substrate 有权
    从衬底分离的单晶半导体层部分的形成

    公开(公告)号：US07622368B2

    公开(公告)日：2009-11-24

    申请号：US11704638

    申请日：2007-02-09

    申请人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

    发明人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

    摘要： A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.

    摘要翻译： 一种用于在中空区域上方形成单晶半导体层部分的方法，包括通过牺牲单晶半导体层和单晶半导体层在活性单晶半导体区域上的选择性外延生长，以及去除牺牲层。 在有源区域被凸起的绝缘层围绕的同时进行外延生长，并且通过由至少部分去除凸起的绝缘层获得的访问来执行牺牲单晶半导体层的去除。

    Process for forming a silicon-based single-crystal portion
    28.
    发明申请
    Process for forming a silicon-based single-crystal portion 有权
    用于形成硅基单晶部分的方法

    公开(公告)号：US20070254451A1

    公开(公告)日：2007-11-01

    申请号：US11788391

    申请日：2007-04-18

    申请人： Didier Dutartre ,  Laurent Rubaldo ,  Alexandre Talbot

    发明人： Didier Dutartre ,  Laurent Rubaldo ,  Alexandre Talbot

    IPC分类号： H01L21/76 ,  H01L21/302

    CPC分类号： H01L21/02381 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262

    摘要： Silicon-based single-crystal portions are produced on a surface of a substrate, selectively in zones where a single-crystal material is initially exposed. To do this, a layer is firstly formed over the entire surface of the substrate, using a silicon precursor of the non-chlorinated hydride type, and under suitable conditions so that the layer is a single-crystal layer in the zones of the substrate where a single-crystal material is initially exposed and amorphous outside these zones. The amorphous portions of the layer are then selectively etched so that only the single-crystal portions of the layer remain on the substrate.

    摘要翻译： 在单晶材料最初暴露的区域选择性地在基板的表面上制造硅基单晶部分。 为此，首先在基板的整个表面上使用非氯化氢化物型的硅前体，并在合适的条件下形成层，使得该层是基板区域中的单晶层， 单晶材料最初在这些区域之外露出和非晶态。 然后选择性地蚀刻该层的非晶部分，使得只有该层的单晶部分保留在基板上。

    Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
    29.
    发明授权
    Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic 失效
    在硅衬底上外延的方法，其包括重掺杂砷的区域

    公开(公告)号：US06776842B2

    公开(公告)日：2004-08-17

    申请号：US09902497

    申请日：2002-01-15

    申请人： Didier Dutartre ,  Patrick Jerier

    发明人： Didier Dutartre ,  Patrick Jerier

    IPC分类号： C30B2502

    CPC分类号： C30B29/06 ,  C23C16/24 ,  C30B25/20

    摘要： The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

    摘要翻译： 本发明涉及一种在硅基板上气相外延沉积硅的方法，该方法包括含有高浓度掺杂剂的区域，其中砷是砷，同时避免了砷的外延层的自掺杂，包括以下步骤：执行第一薄外延 沉积，然后退火; 第一外延沉积和退火的条件和持续时间使得砷扩散长度远低于在第一沉积中形成的层的厚度; 以及对所选择的持续时间进行第二外延沉积以获得期望的总厚度。