Abstract:
Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
Abstract:
A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.
Abstract:
A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.
Abstract:
The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
Abstract:
The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
Abstract:
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.
Abstract:
Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.
Abstract:
The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
Abstract:
A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable material and the outer electrode material contact one another along an interface. Protective material is formed elevationally over the outer electrode material. Dopant is implanted through the protective material into the outer electrode material and the programmable material and across the interface to enhance adhesion of the outer electrode material and the programmable material relative one another across the interface. Memory cells are also disclosed.
Abstract:
The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.