公开(公告)号：US20230397423A1

公开(公告)日：2023-12-07

申请号：US18307698

申请日：2023-04-26

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  Yongjun J. Hu ,  Pavan Reddy Kumar Aella ,  David Ross Economy ,  Brittany L. Kohoutek ,  Amritesh Rai

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A method of forming a microelectronic device includes forming conductive interconnect structures vertically extending through isolation material to conductive contact structures coupled to pillar structures, forming a metal silicide material on the interconnect structures and the first isolation material, forming a conductive material on the metal silicide material, and forming a dielectric material over the conductive material. The method further includes forming openings vertically extending through the dielectric material, the conductive material, the metal silicide material, and the isolation material and forming additional isolation material to extend over remaining portions of the dielectric material and at least partially fill the openings. Related devices and systems are disclosed.

公开(公告)号：US11631811B2

公开(公告)日：2023-04-18

申请号：US17315114

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  Yongjun J. Hu

IPC: H01L45/00

Abstract: Memory devices having electrode structures that increase in resistivity with thermal cycling, and associated systems and methods, are disclosed herein. In some embodiments, a memory device includes a memory element and an electrode structure electrically coupled to the memory element. The electrode structure can include a material comprising a composition of tungsten, silicon, and germanium.

公开(公告)号：US20220020662A1

公开(公告)日：2022-01-20

申请号：US17492185

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US11101171B2

公开(公告)日：2021-08-24

申请号：US16542507

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yongjun J. Hu ,  David A. Kewley ,  Md Zahid Hossain ,  Michael J. Irwin ,  Daniel Billingsley ,  Suresh Ramarajan ,  Robert J. Hanson ,  Biow Hiem Ong ,  Keen Wah Chow

IPC: H01L21/768

Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

公开(公告)号：US20200212046A1

公开(公告)日：2020-07-02

申请号：US16235957

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Kentaro Ishii ,  Yongjun J. Hu ,  Amirhasan Nourbakhsh ,  Durai Vishak Nirmal Ramaswamy ,  Christopher W. Petz ,  Luca Fumagalli

IPC: H01L27/108

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

公开(公告)号：US11984382B2

公开(公告)日：2024-05-14

申请号：US17492185

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3736 ,  H01L21/02186 ,  H01L21/0234 ,  H01L21/768 ,  H01L23/535

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US20230154856A1

公开(公告)日：2023-05-18

申请号：US18157962

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06

CPC classification number: H01L23/5386 ,  H01L23/5385 ,  H01L23/5384 ,  H01L23/53204 ,  H01L21/76877 ,  G11C5/06 ,  G11C5/025 ,  H01L21/76802 ,  H01L27/0688

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220415917A1

公开(公告)日：2022-12-29

申请号：US17822708

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11529

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11527548B2

公开(公告)日：2022-12-13

申请号：US16216088

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： Haoyu Li ,  Everett A. McTeer ,  Christopher W. Petz ,  Yongjun J. Hu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11524 ,  H01L21/28

Abstract: A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.

公开(公告)号：US20220310522A1

公开(公告)日：2022-09-29

申请号：US17209993

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L27/06 ,  G11C5/06 ,  G11C5/02 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.