公开(公告)号：US20200013829A1

公开(公告)日：2020-01-09

申请号：US16575743

申请日：2019-09-19

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Agostino Pirovano ,  Andrea Redaelli

IPC: H01L27/24

Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.

公开(公告)号：US20180315797A1

公开(公告)日：2018-11-01

申请号：US15497503

申请日：2017-04-26

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Agostino Pirovano ,  Andrea Redaelli

IPC: H01L27/24 ,  H01L27/11514

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L27/2427 ,  H01L45/1675

Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.

公开(公告)号：US09990989B2

公开(公告)日：2018-06-05

申请号：US15154410

申请日：2016-05-13

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04

CPC classification number: G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

公开(公告)号：US20240029795A1

公开(公告)日：2024-01-25

申请号：US17868232

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Lifang Xu ,  Harsh Narendrakumar Jain

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises channel-material strings of memory cells extending through insulative tiers and conductive tiers in a memory-array region. The insulative and conductive tiers extend from the memory-array region into a stair-step region. A plurality of stair-step structures is in the stair-step region. The stair-step structures individually comprise two opposing flights of stairs. The stair-step structures comprise an SGD stair-step structure and non-SGD stair-step structures. At least one of the non-SGD stair-step structures has less total stairs than are in individual of multiple others of the non-SGD stair-step structures. Other embodiments, including method, are disclosed.

公开(公告)号：US11783897B2

公开(公告)日：2023-10-10

申请号：US17875001

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

IPC: G11C7/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

公开(公告)号：US20230019954A1

公开(公告)日：2023-01-19

申请号：US17875001

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

公开(公告)号：US20210272615A1

公开(公告)日：2021-09-02

申请号：US17325997

申请日：2021-05-20

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Mattia Robustelli ,  Innocenzo Tortorelli ,  Mario Allegra

IPC: G11C11/16

Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

公开(公告)号：US20200303640A1

公开(公告)日：2020-09-24

申请号：US16877154

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Anna Maria Conti ,  Agostino Pirovano

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.

公开(公告)号：US20200176512A1

公开(公告)日：2020-06-04

申请号：US16785026

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Andrea Redaelli ,  Agostino Pirovano

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

公开(公告)号：US10541364B2

公开(公告)日：2020-01-21

申请号：US15893108

申请日：2018-02-09

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Anna Maria Conti ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.