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    BOOLEAN LOGIC IN A STATE MACHINE LATTICE
    21.
    发明申请
    BOOLEAN LOGIC IN A STATE MACHINE LATTICE 有权
    BOOLEAN逻辑在一个状态机床

    公开(公告)号：US20140077838A1

    公开(公告)日：2014-03-20

    申请号：US14087973

    申请日：2013-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

    IPC: H03K19/20

    CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

    SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE
    22.
    发明申请
    SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE 有权

    公开(公告)号：US20250165265A1

    公开(公告)日：2025-05-22

    申请号：US19025565

    申请日：2025-01-16

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G06F9/448 ,  G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/42

    Abstract: A system includes a primary device comprising a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of first data as a first analysis and to output a result of the first analysis. The system also includes a secondary device coupled to the primary device, wherein the secondary device comprises a second plurality of configurable elements configured to analyze at least a portion of second data received from the primary device as a second analysis and to output a result of the second analysis, wherein the primary device

    APPARATUSES AND METHODS FOR MULTIPLE TYPES OF ALERT ALONG ALERT BUS
    23.
    发明申请
    APPARATUSES AND METHODS FOR MULTIPLE TYPES OF ALERT ALONG ALERT BUS 有权

    公开(公告)号：US20240428842A1

    公开(公告)日：2024-12-26

    申请号：US18743309

    申请日：2024-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Randall J. Rooney ,  David R. Brown ,  Michael A. Shore ,  Kang-Yong Kim

    IPC: G11C11/406 ,  G11C11/4076

    Abstract: Apparatuses, systems, and methods for multiple types of alert along an alert bus. A memory device may detect multiple types of alert and use an alert signal along an alert bus to signal a controller of these alerts. Different pulse widths of the alert signal may be used to indicate the type of alert. For example if the alert signal is at an active level between a first duration and a second duration, it may indicate a first type of alert, if the alert signal is active between a third duration and a fourth duration, it may indicate a second type of alert. If the alert signal remains active for longer than a threshold amount of time, it may indicate a third type of alert.

    System and method to control memory error detection with automatic disabling
    25.
    发明授权
    System and method to control memory error detection with automatic disabling 有权

    公开(公告)号：US12019512B2

    公开(公告)日：2024-06-25

    申请号：US17829576

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Thanh K. Mai ,  Parthasarathy Gajapathy ,  David R. Brown

    IPC: G06F11/10

    CPC classification number: G06F11/1004

    Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

    SYSTEMS AND METHODS FOR MEMORY REFRESH
    27.
    发明申请
    SYSTEMS AND METHODS FOR MEMORY REFRESH 有权

    公开(公告)号：US20220068363A1

    公开(公告)日：2022-03-03

    申请号：US17002316

    申请日：2020-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Joo-Sang Lee ,  David R. Brown

    IPC: G11C11/406 ,  G11C11/4076 ,  G11C29/44

    Abstract: A memory device includes a memory bank having a set of word lines, a bank control block coupled to the memory bank, wherein the bank control block when in operation provides timing control and data control to facilitate execution of commands to and from the memory bank and a command decoder coupled to the bank control block. The command decoder when in operation transmits to the bank control bank a refresh (REF) command associated with a first pump to refresh a memory cell of the memory bank and a row hammer refresh (RHR) command associated with a second pump to refresh a second memory cell of the memory bank in conjunction with a refresh operation, and the bank control block when in operation transmits a first control signal to the command decoder to determine which automatic error check and scrub (AECS) mode operation is selected.

    METHODS AND SYSTEMS FOR DATA ANALYSIS IN A STATE MACHINE
    29.
    发明申请
    METHODS AND SYSTEMS FOR DATA ANALYSIS IN A STATE MACHINE 审中-公开

    公开(公告)号：US20200334533A1

    公开(公告)日：2020-10-22

    申请号：US16917221

    申请日：2020-06-30

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B Noyes

    IPC: G06N3/08 ,  G06K9/00 ,  G06N3/063

    Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

    System and method for individual addressing
    30.
    发明授权
    System and method for individual addressing 有权

    公开(公告)号：US10789182B2

    公开(公告)日：2020-09-29

    申请号：US16726523

    申请日：2019-12-24

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

    IPC: G06F15/00 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

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