公开(公告)号：US20240069765A1

公开(公告)日：2024-02-29

申请号：US17894794

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

公开(公告)号：US20230307053A1

公开(公告)日：2023-09-28

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/26 ,  G11C16/102 ,  G11C16/0433

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US11763900B2

公开(公告)日：2023-09-19

申请号：US17951754

申请日：2022-09-23

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/26 ,  G11C16/34 ,  G11C7/10 ,  G11C16/10

CPC classification number: G11C16/3436 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/10 ,  G11C16/26

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US11742034B2

公开(公告)日：2023-08-29

申请号：US17745415

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Lawrence Celso Miranda

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

公开(公告)号：US11735268B2

公开(公告)日：2023-08-22

申请号：US17382619

申请日：2021-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Siciliani ,  Floriano Montemurro ,  Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/14 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/102 ,  G11C16/26

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

公开(公告)号：US20230063057A1

公开(公告)日：2023-03-02

申请号：US17458835

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

IPC: G06F3/06

Abstract: A method includes detecting an occurrence of an event associated with a memory sub-system comprising blocks of non-volatile memory cells. The method further includes responsive to detecting the occurrence of the event, providing signaling to disable at least a portion of the memory sub-system, an interface coupled to the memory sub-system, or both.

公开(公告)号：US20230062445A1

公开(公告)日：2023-03-02

申请号：US17682089

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Violante Moschiano ,  Jeffrey S. McNeil ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.

公开(公告)号：US20220165340A1

公开(公告)日：2022-05-26

申请号：US17102876

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C7/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US20220138108A1

公开(公告)日：2022-05-05

申请号：US17452764

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Yoav Weinberg

IPC: G06F12/0882 ,  G06F9/30 ,  G06F12/0817 ,  G06F12/0891

Abstract: A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a cache release command indicating that data associated with a first subset of the plurality of memory planes and pertaining to a previous read command was received by the requestor. Responsive to the cache release command, the control logic returns to the requestor, data from the cache register and associated with a second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to a subsequent read command into the cache register.

公开(公告)号：US11238937B2

公开(公告)日：2022-02-01

申请号：US16935740

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

Abstract: Memories having a controller configured to apply a particular multi-step programming pulse to a selected access line of a programming operation, enable for programming memory cells that have a particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a first threshold voltage level while applying a first step of a multi-step programming pulse to the selected access line, and enable for programming memory cells that have the particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a second threshold voltage level and higher than the first threshold voltage level while applying a second step of the multi-step programming pulse, lower than the first step of the multi-step programming pulse, to the selected access line.