公开(公告)号：US20230410895A1

公开(公告)日：2023-12-21

申请号：US17842492

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Soichi Sugiura

IPC: G11C11/4097 ,  G11C11/4091

CPC classification number: G11C11/4097 ,  G11C11/4091

Abstract: An apparatus may include a first matrix comprising a first plurality of digit lines, a second matrix comprising a second plurality of digit lines, a plurality of sense amplifiers, and a plurality of selector circuits. Each selector circuit of the plurality of selector circuits may be configured to selectively couple a respective sense amplifier to either a first digit line of the first plurality of digit lines or a second digit line of the second plurality of digit lines.

公开(公告)号：US11776625B2

公开(公告)日：2023-10-03

申请号：US17496667

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Hari Giduturi

IPC: G11C13/00 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C13/0038 ,  G11C5/145 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).

公开(公告)号：US11417375B2

公开(公告)日：2022-08-16

申请号：US17085154

申请日：2020-10-30

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Jin Seung Son ,  Andrea Ghetti

IPC: G11C8/08 ,  G11C7/12

Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

公开(公告)号：US11380394B2

公开(公告)日：2022-07-05

申请号：US17158984

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Michel Ibrahim Ishac

IPC: G11C11/419 ,  G11C13/00

Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.

公开(公告)号：US20220093190A1

公开(公告)日：2022-03-24

申请号：US17487792

申请日：2021-09-28

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Hongmei Wang ,  Mingdong Cui

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

公开(公告)号：US20210193314A1

公开(公告)日：2021-06-24

申请号：US16989749

申请日：2020-08-10

Applicant: Micron Technology, Inc.

Inventor： Gitanjali T. Ghosh ,  Irene K. Thompson ,  Jessica M. Maderos ,  Hongmei Wang ,  Fatma Arzum Simsek-Ege ,  Kathryn H. Russo

IPC: G16H40/67 ,  G16H40/63

Abstract: Systems, apparatuses, and methods related to medical device data analysis are described. In some examples, a medical device is implanted in a user of the medical device and the data generated by the medical device is not easily accessible to the user. In an example, a controller can be configured to receive, by a mobile device coupled to a medical device, data from the medical device, where the data is a part of a baseline dataset related to the medical device. The controller can be configured to receive different data from the medical device, where the different data is received from the medical device as the different data is generated by the medical device, analyze the data from the medical device and the different data generated by the medical device, and perform an action based on the analyzed data and the different data generated by the medical device.

公开(公告)号：US20200350371A1

公开(公告)日：2020-11-05

申请号：US16400943

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Lorenzo Fratin ,  Hongmei Wang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L21/66

Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

公开(公告)号：US10777291B2

公开(公告)日：2020-09-15

申请号：US16284491

申请日：2019-02-25

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Hongmei Wang

IPC: G11C13/00 ,  G11C29/00 ,  H01L27/24 ,  H01L45/00 ,  G11C29/52

Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

公开(公告)号：US09171863B2

公开(公告)日：2015-10-27

申请号：US14543063

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/16

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/16 ,  H01L29/7889 ,  H01L29/7926

Abstract: Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.

Abstract translation: 各种实施例包括包括沿半导体材料层形成的存储单元串的方法和装置。 一种这样的装置包括由许多级别的单晶硅和多种电介质材料构成的叠层。 硅层中的每一层都通过介电材料的水平与相邻硅层分离。 沿着硅层形成存储单元的串。 公开了附加的装置和方法。

公开(公告)号：US12020745B2

公开(公告)日：2024-06-25

申请号：US17842492

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Soichi Sugiura

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C11/4097 ,  G11C11/4091

Abstract: An apparatus may include a first matrix comprising a first plurality of digit lines, a second matrix comprising a second plurality of digit lines, a plurality of sense amplifiers, and a plurality of selector circuits. Each selector circuit of the plurality of selector circuits may be configured to selectively couple a respective sense amplifier to either a first digit line of the first plurality of digit lines or a second digit line of the second plurality of digit lines.