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    COMPARISON OPERATIONS IN MEMORY
    21.
    发明申请
    COMPARISON OPERATIONS IN MEMORY 审中-公开

    公开(公告)号：US20200219577A1

    公开(公告)日：2020-07-09

    申请号：US16818694

    申请日：2020-03-13

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C29/12 ,  G11C29/32 ,  G11C29/14 ,  G06F9/38 ,  G06F9/30 ,  G11C7/06 ,  G06F15/78

    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

    Comparison operations in memory
    22.
    发明授权
    Comparison operations in memory 有权

    公开(公告)号：US10593418B2

    公开(公告)日：2020-03-17

    申请号：US15822748

    申请日：2017-11-27

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C29/12 ,  G06F15/78 ,  G06F9/38 ,  G11C7/06 ,  G06F9/30 ,  G11C29/14 ,  G11C29/32 ,  G11C16/10 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4091

    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

    Comparison operations in memory
    24.
    发明授权
    Comparison operations in memory 有权

    公开(公告)号：US09940985B2

    公开(公告)日：2018-04-10

    申请号：US15692959

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C7/06 ,  G11C8/10

    CPC classification number: G11C7/22 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/12 ,  G11C8/10

    Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

    Data shift by elements of a vector in memory
    25.
    发明授权
    Data shift by elements of a vector in memory 有权

    公开(公告)号：US09928887B2

    公开(公告)日：2018-03-27

    申请号：US15457339

    申请日：2017-03-13

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096

    CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

    Signed division in memory
    26.
    发明授权
    Signed division in memory 有权

    公开(公告)号：US09910637B2

    公开(公告)日：2018-03-06

    申请号：US15073191

    申请日：2016-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G06F7/535

    CPC classification number: G06F7/535

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.

    Division operations on variable length elements in memory
    27.
    发明授权
    Division operations on variable length elements in memory 有权

    公开(公告)号：US09898253B2

    公开(公告)日：2018-02-20

    申请号：US15063986

    申请日：2016-03-08

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari ,  Kyle B. Wheeler

    IPC: G06F7/535 ,  G11C7/10 ,  G11C7/06 ,  G11C11/4076 ,  G11C11/4091

    CPC classification number: G06F7/535 ,  G06F2207/535 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing variable bit-length division operations in a memory. An example method comprises performing a variable length division operation on a first vector comprising variable length elements representing a number of dividends and stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second vector comprising variable length elements representing a number of divisors stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include dividing the first vector by the second vector by performing a number of operations. The method can include performing at least one of the number of operations without transferring data via an input/output (I/O) line.

    LOOP STRUCTURE FOR OPERATIONS IN MEMORY
    28.
    发明申请
    LOOP STRUCTURE FOR OPERATIONS IN MEMORY 有权
    内存中操作的环路结构

    公开(公告)号：US20160225422A1

    公开(公告)日：2016-08-04

    申请号：US15013269

    申请日：2016-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari ,  Kyle Wheeler

    IPC: G11C8/04 ,  G11C7/00

    CPC classification number: G11C7/1012 ,  G11C7/00 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/12 ,  G11C8/04 ,  G11C11/4091 ,  G11C11/4094

    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

    Abstract translation: 本公开的示例提供了与在存储器中执行的操作执行循环结构相关的装置和方法。 示例性装置还可以包括控制器，其被配置为使得感测电路经由环路结构遍历多个第一元件和多个第二元件，以使用多个第一元件和多个第二元件执行操作，其中a 与循环结构相关联的条件语句用于确定存储为迭代器掩码的多个比特中的至少一个是否具有特定的比特值。 示例性装置还可以包括可控制的感测电路，以在循环结构的每次迭代时使用迭代器掩码执行移位操作，并且在循环结构的每次迭代时使用迭代器掩码执行AND运算。

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