公开(公告)号：US10128183B1

公开(公告)日：2018-11-13

申请号：US15926505

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US20180323142A1

公开(公告)日：2018-11-08

申请号：US15926505

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10885

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US20160300842A1

公开(公告)日：2016-10-13

申请号：US14681884

申请日：2015-04-08

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir ,  Dylan R. MacMaster

IPC: H01L27/108 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L27/10805 ,  H01L21/02068 ,  H01L21/31111 ,  H01L21/743 ,  H01L21/762 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649 ,  H01L29/7391

Abstract: A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars. Semiconductor device structures and additional methods are also described.

Abstract translation: 形成用于半导体器件结构的触点的方法包括形成延伸到相邻的半导体柱中的接触孔，并形成氮化物覆盖的电极的氮化物材料。 复合结构形成在接触孔内并且包括在接触孔的侧壁上的氧化物结构和氧化物结构上的氮化物结构。 导电结构形成在复合结构的内侧壁上。 附加的氮化物封盖的电极形成在导电结构之上并垂直于氮化物封盖的电极延伸。 一对氮化物间隔物形成在另外的氮化物覆盖的电极的相对侧壁上，并且通过延伸到相邻半导体柱的一部分的上表面的孔与相邻的氮化物间隔物相分离。 去除部分氧化物结构以暴露相邻半导体柱的部分的侧壁。 还描述了半导体器件结构和附加方法。

公开(公告)号：US20160155745A1

公开(公告)日：2016-06-02

申请号：US15005360

申请日：2016-01-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/10823 ,  H01L21/76232 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/66621 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract translation: 一组凹进的存取栅极线包括其间具有介电沟槽隔离材料的有源区域区域。 沟槽隔离材料包括延伸到有源区域区域的材料的最外表面下方的各个有源区域的相对端的电介质突起。 有源区域材料在电介质突起上是垂直的。 嵌入式栅极线分别横跨有源区域区域延伸并且在电介质沟槽隔离材料内的紧邻端到端相邻有源区域区域的端部之间延伸。 公开了其他阵列，方法也是如此。

公开(公告)号：US20160104709A1

公开(公告)日：2016-04-14

申请号：US14511371

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/108 ,  G11C11/407

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

公开(公告)号：US20150243748A1

公开(公告)日：2015-08-27

申请号：US14190807

申请日：2014-02-26

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Haitao Liu ,  Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/7827

Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.

Abstract translation: 垂直存取装置包括半导体基底，其包括第一源极/漏极区域，从半导体基底垂直延伸的半导体柱和邻近半导体支柱的侧壁的栅电极。 半导体柱包括覆盖第一源极/漏极区域的沟道区域和覆盖沟道区域的第二源极/漏极区域。 半导体柱的相对的侧壁不与栅电极或另一栅电极相邻。 还描述了半导体器件结构，形成垂直访问器件的方法以及形成半导体结构的方法。