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公开(公告)号：US20250060876A1
公开(公告)日：2025-02-20
申请号：US18933218
申请日：2024-10-31
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Ying Yu Tai
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on memory component reliabilities. The controller can access configuration data to determine a reliability grade associated with individual groups of the memory components. The controller can then adaptively select between different media management operations based on the reliability grade associated with each individual group of the memory components.
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公开(公告)号：US12189960B2
公开(公告)日：2025-01-07
申请号：US17954023
申请日：2022-09-27
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
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公开(公告)号：US11907563B2
公开(公告)日：2024-02-20
申请号：US17940751
申请日：2022-09-08
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Chih-Kuo Kao , Ying Yu Tai , Jiangli Zhu
CPC classification number: G06F3/0647 , G06F1/04 , G06F3/0604 , G06F3/0659 , G06F3/0673
Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
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公开(公告)号：US11874779B2
公开(公告)日：2024-01-16
申请号：US17112748
申请日：2020-12-04
Applicant: Micron Technology, Inc.
Inventor： Wei Wang , Jiangli Zhu , Ying Yu Tai , Samir Mittal
CPC classification number: G06F13/1642 , G06F3/061 , G06F3/0659 , G06F3/0671 , G11C7/1045 , G06F2213/16
Abstract: A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus.
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公开(公告)号：US11714697B2
公开(公告)日：2023-08-01
申请号：US17531091
申请日：2021-11-19
Applicant: Micron Technology, Inc.
Inventor： Jiangli Zhu , Ying Yu Tai , Fangfang Zhu , Wei Wang
CPC classification number: G06F11/0772 , G06F9/30101 , G06F9/544 , G06F11/073 , G06F11/076 , G06F11/1044 , G06F11/1068 , G06F11/1441 , G06F11/3037
Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.
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Patent Agency Ranking
公开(公告)号：US11681472B2
公开(公告)日：2023-06-20
申请号：US17492181
申请日：2021-10-01
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F11/1004 , G06F13/1668
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
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公开(公告)号：US11615214B2
公开(公告)日：2023-03-28
申请号：US16913748
申请日：2020-06-26
Applicant: Micron Technology, Inc.
Inventor： Juane Li , Jiangli Zhu , Ying Yu Tai
Abstract: Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.
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28.发明申请公开(公告)号：US20220206941A1
公开(公告)日：2022-06-30
申请号：US17698424
申请日：2022-03-18
Applicant: Micron Technology, Inc.
Inventor： Ning Chen , Jiangli Zhu , Ying Yu Tai
Abstract: A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units. Data located in data management units subsequent to the second indicator remain located in data management units of the source group of data management units and have not been copied to the destination group of data management units.
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公开(公告)号：US11288013B2
公开(公告)日：2022-03-29
申请号：US16916934
申请日：2020-06-30
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Jiangli Zhu , Ying Yu Tai , Wei Wang
Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.
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公开(公告)号：US20220019383A1
公开(公告)日：2022-01-20
申请号：US17492181
申请日：2021-10-01
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
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