公开(公告)号：US11750218B2

公开(公告)日：2023-09-05

申请号：US17831357

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/1128 ,  G06F11/1076

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

公开(公告)号：US11693732B2

公开(公告)日：2023-07-04

申请号：US17014771

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz ,  Lance W. Dover ,  Yoav Weinberg

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/1408 ,  G06F13/4221 ,  G06F2212/7201

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

公开(公告)号：US11650931B2

公开(公告)日：2023-05-16

申请号：US17234062

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Yoav Weinberg ,  Alberto Sassara ,  Paolo Papa ,  Luigi Esposito ,  Giuseppe D'Eliseo ,  Angelo Della Monica ,  Massimo Iaculo

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/7201

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

公开(公告)号：US11500791B2

公开(公告)日：2022-11-15

申请号：US17117933

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

IPC: G06F13/16 ,  G06F1/26

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

公开(公告)号：US11151052B2

公开(公告)日：2021-10-19

申请号：US16713552

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Laculo ,  Lalla Fatima Drissi

IPC: G06F12/1009

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

公开(公告)号：US11146291B2

公开(公告)日：2021-10-12

申请号：US16806777

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00 ,  H03M13/11 ,  H03M13/09 ,  H03M13/29 ,  H03M13/15

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative LDPC correction process, wherein at least one iteration after a first iteration in the LDPC correction process uses a criterion based at least partially on a previous iteration or partial iteration.

公开(公告)号：US20210240633A1

公开(公告)日：2021-08-05

申请号：US17234062

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Yoav Weinberg ,  Alberto Sassara ,  Paolo Papa ,  Luigi Esposito ,  Giuseppe D'Eliseo ,  Angelo Della Monica ,  Massimo Iaculo

IPC: G06F12/1009

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

公开(公告)号：US12292795B2

公开(公告)日：2025-05-06

申请号：US18416967

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Tal Sharifie ,  Chandrakanth Rapalli ,  Yoav Weinberg

IPC: G06F11/10 ,  G06F11/07

Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system receives data units from a host device. A first controller of the memory system generates a protocol unit using the data units. A second controller of the memory system generates a data storage unit using data from the protocol unit, and stores the data unit to a memory device. The memory system performs error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system, for a write operation, re-requests data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.

公开(公告)号：US20250077455A1

公开(公告)日：2025-03-06

申请号：US18951879

申请日：2024-11-19

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

IPC: G06F13/30 ,  G06F13/16

Abstract: Operations include determining, based on a period of time during which a logical level of the signal line is maintained at a first logical level, that a data transfer to the memory array is being suspended, determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level, and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.

公开(公告)号：US12243600B2

公开(公告)日：2025-03-04

申请号：US18583510

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Evgeni Bassin

IPC: G11C29/02 ,  G11C5/14

Abstract: Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.