公开(公告)号：US5882998A

公开(公告)日：1999-03-16

申请号：US55018

申请日：1998-04-03

申请人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

发明人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC分类号： H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

摘要翻译： 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5764563A

公开(公告)日：1998-06-09

申请号：US723007

申请日：1996-09-30

申请人： Harlan Lee Sur, Jr. ,  Subhas Bothra

发明人： Harlan Lee Sur, Jr. ,  Subhas Bothra

IPC分类号： G11C11/412 ,  H01L21/02 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L28/20 ,  G11C11/412 ,  H01L27/1112

摘要： A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

摘要翻译： 用于制造用于集成电路的电阻负载结构的电阻负载结构和方法包括使用非晶硅“反熔丝”材料。 电阻负载结构可用于SRAM单元中，以提供负载以抵消SRAM单元的两个下拉晶体管和两个通过晶体管的漏极处的电荷泄漏。 有利地通过在导电通孔上沉积非晶硅垫来形成电阻负载结构，并且通过调节非晶硅垫的厚度并改变下面的导电通孔的直径来控制电阻负载结构的电阻。

公开(公告)号：US07489221B2

公开(公告)日：2009-02-10

申请号：US11504073

申请日：2006-08-15

申请人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

发明人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

摘要翻译： 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US06411367B1

公开(公告)日：2002-06-25

申请号：US09280174

申请日：1999-03-29

申请人： Daniel C. Baker ,  Subhas Bothra ,  Satyendra Sethi

发明人： Daniel C. Baker ,  Subhas Bothra ,  Satyendra Sethi

IPC分类号： G03B2754

CPC分类号： G03F7/70108 ,  G02B27/58 ,  G03F7/70225

摘要： A system and method is disclosed for enhancing an optical lithography process by capturing light diffracted from a mask having features to be exposed onto a wafer. In one embodiment, a system of the present invention has in place a mask, a wafer and a reduction lens such that the reduction lens is placed between the mask and the wafer in order to direct and expose the mask's features onto the wafer. Furthermore, a reflective member is disposed proximate to the reduction lens. In order to achieve finer resolution of the mask image on the wafer, this reflective member captures diffracted light diffracting beyond the reduction lens and redirects the diffracted light to pass through the reduction lens such that the diffracted light is redirected onto the wafer. In so doing, the reflective member resolves the mask image on the wafer in more detail than is possible by an optical lithography process using no such reflective member.

摘要翻译： 公开了一种用于通过捕获从具有要暴露于晶片上的特征的掩模衍射的光来增强光刻工艺的系统和方法。 在一个实施例中，本发明的系统具有掩模，晶片和还原透镜，使得将还原透镜放置在掩模和晶片之间，以便将掩模的特征引导并暴露在晶片上。 此外，反射构件设置在靠近减速透镜的位置。 为了获得晶片上的掩模图像的更精细的分辨率，该反射构件捕获衍射光超出了还原透镜的衍射光，并且重定向衍射光以通过还原透镜，使得衍射光被重定向到晶片上。 在这样做时，反射构件比不使用这种反射构件的光学光刻工艺更可靠地解决晶片上的掩模图像。

公开(公告)号：US06399432B1

公开(公告)日：2002-06-04

申请号：US09199203

申请日：1998-11-24

申请人： Tammy Zheng ,  Subhas Bothra

发明人： Tammy Zheng ,  Subhas Bothra

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L21/28035

摘要： For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

摘要翻译： 为了与亚微米CMOS技术一起使用，栅极蚀刻工艺改善了蚀刻轮廓的控制。 栅堆叠利用N型或P型掺杂的非晶或多晶硅来提高器件性能。 然而，N型相对于P型非晶或多晶硅材料的不同蚀刻特性可导致邻近栅极叠层边缘的底层薄栅极氧化物的局部穿透，特别是在N掺杂有源区中。 根据一个示例实施例，通过将具有未掺杂的非晶或多晶硅的栅极堆叠构建成所需的配置来避免该局部突破（“微切割”），用介电层掩蔽栅极堆叠，平坦化介电层，然后将N 型或P型物质进入选定的栅极堆叠。

公开(公告)号：US06372522B1

公开(公告)日：2002-04-16

申请号：US09631059

申请日：2000-08-01

申请人： Milind Ganesh Weling ,  Subhas Bothra ,  Satyendra Sethi

发明人： Milind Ganesh Weling ,  Subhas Bothra ,  Satyendra Sethi

IPC分类号： H01L2100

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit die. The first and second interconnect elements are couple via an interconnect link. An anti-reflective layer is disposed on a surface above the interconnect link. The anti-reflective layer is configured to increase an amount of laser energy absorbed by the interconnect link in order to fuse the interconnect link, and thereby repair the integrated circuit die.

摘要翻译： 一种用于在半导体集成电路管芯中使用激光能量的可修复互连链路的系统。 集成电路管芯被制造成包括多个互连连接。 至少第一和第二互连元件包括在集成电路管芯中。 第一和第二互连元件经由互连链路耦合。 抗反射层设置在互连连接件上的表面上。 防反射层被配置为增加由互连链路吸收的激光能量的量，以便熔断互连链路，从而修复集成电路管芯。

公开(公告)号：US06355969B1

公开(公告)日：2002-03-12

申请号：US09405043

申请日：1999-09-27

申请人： Stephen L. Skala ,  Subhas Bothra

发明人： Stephen L. Skala ,  Subhas Bothra

IPC分类号： H01L2144

CPC分类号： H01L23/5256 ,  H01L21/76879 ,  H01L21/76892 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making, and a programmable structure for use in a semiconductor chip is provided. The method includes forming a lower metallization layer, and forming an upper metallization layer. The upper metallization layer has a first portion and a second portion. An eroded via is formed between the lower metallization layer and the first portion of the upper metallization layer, and a conductive via is formed between the lower metallization layer and the second portion of the upper metallization layer. The method then includes applying a current between the lower metallization layer and the second portion of the upper metallization layer. The current is configured to cause electromigration in the lower metallization layer such that some of the electromigration fills the eroded via between the lower metallization layer and first portion of the upper metallization layer. The current, if programming is desired, is applied from pads of the semiconductor chip either directly or by way of a programming circuit.

摘要翻译： 提供了制造方法和用于半导体芯片的可编程结构。 该方法包括形成下金属化层，并形成上金属化层。 上金属化层具有第一部分和第二部分。 在下金属化层和上金属化层的第一部分之间形成侵蚀通孔，并且在下金属化层和上金属化层的第二部分之间形成导电通孔。 该方法然后包括在下部金属化层和上部金属化层的第二部分之间施加电流。 电流被配置为在下金属化层中引起电迁移，使得一些电迁移填充下金属化层和上金属化层的第一部分之间的侵蚀通孔。 如果需要编程，则电流直接地或通过编程电路施加于半导体芯片的焊盘。

公开(公告)号：US06327695B1

公开(公告)日：2001-12-04

申请号：US09451668

申请日：1999-11-30

申请人： Subhas Bothra ,  Paul R. Findley

发明人： Subhas Bothra ,  Paul R. Findley

IPC分类号： G06F1750

CPC分类号： H01L21/76224 ,  H01L21/763

摘要： Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilicon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.

摘要翻译： 公开了用于抑制电源感应噪声的片上电容结构网络，制造方法以及用于设计片上电容结构的系统。 网络包括分散在具有多个有源区域的集成电路设计中的多个虚拟有源区域。 多个虚拟有源区域与多个有源区域分开至少一个膨胀距离。 该网络还包括虚拟多晶硅线路网络，其被配置为覆盖所选择的虚拟有源区域。 覆盖所选择的虚拟有源区域的虚拟多晶硅线的网络用作虚拟栅极。 在本实施例中，所选择的虚拟有源区和覆盖所选择的虚拟有源区的虚拟多晶硅线形成片上电容结构的网络。

公开(公告)号：US06303192B1

公开(公告)日：2001-10-16

申请号：US09121180

申请日：1998-07-22

申请人： Rao V. Annapragada ,  Tekle M. Tafari ,  Subhas Bothra

发明人： Rao V. Annapragada ,  Tekle M. Tafari ,  Subhas Bothra

IPC分类号： C23C1416

CPC分类号： H01L21/02137 ,  C23C16/0272 ,  C23C16/505 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3122 ,  H01L21/316 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO2 skin on the methyl compound spin on glass layer and then treated again by plasma-deposition to form a cap layer which adheres to the SiO2 skin.

摘要翻译： 一种制造多层集成电路结构的方法，包括在衬底上沉积甲基化合物旋涂在玻璃层上。 通过等离子体沉积处理玻璃层上的旋涂，在玻璃层上的甲基化合物旋涂上形成SiO 2皮肤，然后通过等离子体沉积再次处理以形成粘附于SiO 2皮肤的盖层。

公开(公告)号：US06297557B1

公开(公告)日：2001-10-02

申请号：US09134070

申请日：1998-08-13

申请人： Subhas Bothra

发明人： Subhas Bothra

IPC分类号： H01L2348

CPC分类号： H01L21/76876 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

摘要翻译： 公开了一种用于半导体互连结构的铝填充通孔。 半导体互连结构的铝填充通孔包括位于第一介电层上的第一图案化金属化层。 覆盖第一图案化金属化层和第一介电层的第二电介质层。 通过第二介电层限定并与第一图案化金属化层接触的铝填充通孔。 铝填充的通孔在铝填充的通孔的最上部具有与第二介电层基本平齐的电迁移阻挡帽。 电迁移阻挡盖的厚度介于约500埃至约2500埃之间。