公开(公告)号：US5511021A

公开(公告)日：1996-04-23

申请号：US394171

申请日：1995-02-22

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C11/40

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/10

摘要： Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that has a forward-biased source-to-substrate junction and a reverse-biased drain-to-substrate junction. During programming, the bias conditions form substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the substrate hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the substrate hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

摘要翻译： 可以通过将相应数量的编程电压中的一个应用于具有正向偏置的源到衬底结和反向偏置漏极的存储器单元的存储器单元的控制栅极来将多个逻辑电平编程到单个EPROM或闪存存储单元中 到底物结合。 在编程期间，偏置条件形成衬底热电子，除了沟道热电子之外，积聚在浮动栅极上。 通过利用基板热电子，可以在编程期间利用低得多的控制栅极电压。 然而，更重要的是，一旦通道热电子停止存在，衬底热电子和空穴会聚到与编程期间使用的控制栅极电压和单元的编程阈值电压有关的稳定电荷。

公开(公告)号：US5908311A

公开(公告)日：1999-06-01

申请号：US690203

申请日：1996-07-25

申请人： Min-hwa Chi ,  Chih-sieh Teng ,  Albert Bergemont

发明人： Min-hwa Chi ,  Chih-sieh Teng ,  Albert Bergemont

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow. The FLASH EPROM cells are formed as single-transistor memory cells that operate on low to very-low voltages.

摘要翻译： 在单个集成CMOS工艺流程中形成包括三伏MOS晶体管，五伏MOS晶体管，FLASH EPROM单元，多晶硅电阻和双重多晶硅电容器的CMOS器件。 FLASH EPROM单元形成为在低至非常低的电压下工作的单晶体管存储单元。

公开(公告)号：US5814856A

公开(公告)日：1998-09-29

申请号：US857156

申请日：1997-05-15

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L29/7881 ,  H01L2924/0002

摘要： A MOSFET structure that utilizes self-aligned polysilicon and/or buried diffusion lines for coupling capacitors, provides a threshold voltage V.sub.T that is tunable from the control gate from positive (enhancement) to negative (depletion) by applying V.sub.cc to the bias gate and carefully designing the coupling ratio of the control gate and the bias gate. This scheme provides multiple V.sub.T 's on-chip without process complexity.

摘要翻译： 利用自对准多晶硅和/或用于耦合电容器的掩埋扩散线的MOSFET结构通过将Vcc施加到偏置栅极并且仔细地提供阈值电压VT，其可以从控制栅极从正（增强）到负（耗尽）可调 设计控制栅极和偏置栅极的耦合比。 该方案提供了多个VT芯片，无需过程复杂性。

公开(公告)号：US5753954A

公开(公告)日：1998-05-19

申请号：US684410

申请日：1996-07-19

申请人： Min-hwa Chi ,  Albert Bergemont

发明人： Min-hwa Chi ,  Albert Bergemont

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/7881

摘要： A single-poly neuron transistor is formed by utilizing a series of doped substrate regions in lieu of the input gates that are conventionally used to form neuron transistors. With conventional neuron transistors, the input gates are isolated from the floating gate by a layer of interpoly dielectric. In the present invention, the series of doped substrate regions are isolated from the floating gate by a layer of gate oxide.

摘要翻译： 通过利用一系列掺杂的衬底区域代替通常用于形成神经元晶体管的输入门来形成单聚聚神经元晶体管。 使用传统的神经元晶体管，输入栅极通过一层多晶硅电介质与浮动栅极隔离。 在本发明中，通过栅极氧化物层将一系列掺杂衬底区域从浮置栅极隔离开来。

公开(公告)号：US08264863B2

公开(公告)日：2012-09-11

申请号：US12869941

申请日：2010-08-27

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/22

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

摘要翻译： 本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。 纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件 在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

公开(公告)号：US20110063888A1

公开(公告)日：2011-03-17

申请号：US12861622

申请日：2010-08-23

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0475 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2436

摘要： A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell.

摘要翻译： 随机存取存储器包括以位线和字线排列的多个存储单元。 每个存储单元包括包括栅极，源极和漏极的绿色晶体管（gFET）; 开关电阻器，包括第一端子和第二端子; 以及包括第三端子和第四端子的参考电阻器。 开关电阻器和第三端子的第一端子连接到位线，开关电阻器的第二端子连接到gFET的第一源极，参考电阻器的第四端子连接到第二源极 gFET和gFET的栅极连接到字线。 操作RRAM的方法包括写入操作和读取操作。写入操作包括以下步骤：向位线施加第一电压以在gFET的位线和漏极之间执行大的电压差，施加 第二电压到gFET的栅极，瞬时导通gFET，并且大电流脉冲流过开关电阻器以改变电阻状态。 读取操作包括以下步骤：将第三电压施加到位线，以在gFET的位线和漏极之间执行小的电压差，向字线施加第二电压以导通gFET;以及 将通过开关电阻的电流与通过参考电阻的电流进行比较，以读取存储在存储单元中的数据。

公开(公告)号：US6088058A

公开(公告)日：2000-07-11

申请号：US865569

申请日：1997-05-29

申请人： Carver A. Mead ,  Tobi Delbruck ,  Min-hwa Chi

发明人： Carver A. Mead ,  Tobi Delbruck ,  Min-hwa Chi

IPC分类号： H04N5/353 ,  H04N5/359 ,  H04N5/369 ,  H04N5/374 ,  H04N3/14 ,  G03B7/00 ,  H04N5/335 ,  H04N9/083

CPC分类号： H04N5/3532 ,  H04N5/353 ,  H04N5/3591 ,  H04N5/3594 ,  H04N5/3741

摘要： An imaging array having overflow protection and electronic shuttering features is realized without an increase in pixel complexity. Overflow protection is provided by pulsing each row of the imager with a small overflow pulse during the sense amplifier reset phase. An electronic shutter is realized using a modified version of the pixel readout timing. The shutter provides sub-frame exposure by restricting the number of line-times a pixel is allowed to integrate. For a full-frame exposure, each pixel is read out once per frame; during readout of the other rows of the array, the pixel integrates. For subframe exposure, the pixel is continually reset, using a shutter pulse applied to the row lines during sense amplifier reset, until a certain number of rows (line-times) before it is to be read out. The pixel then is allowed to integrate until it is read out normally.

摘要翻译： 实现了具有溢出保护和电子快门功能的成像阵列，而不增加像素复杂度。 通过在感测放大器复位阶段期间使成像器的每行脉冲具有小的溢出脉冲来提供溢出保护。 使用像素读出定时的修改版本来实现电子快门。 快门通过限制允许像素集成的行数的次数来提供子帧曝光。 对于全帧曝光，每个像素每帧读出一次; 在读出阵列的其他行期间，像素被整合。 对于子帧曝光，使用在读出放大器复位期间施加到行线的快门脉冲，直到要读出之前的一定数量的行（行时间），像素被连续复位。 然后允许像素整合，直到它被正常读出。

公开(公告)号：US20110090731A1

公开(公告)日：2011-04-21

申请号：US12869941

申请日：2010-08-27

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/22 ,  H01L27/12

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

摘要翻译： 本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。 纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件 在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

公开(公告)号：US06288943B1

公开(公告)日：2001-09-11

申请号：US09614411

申请日：2000-07-12

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： G11C1604

CPC分类号： B82Y10/00 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/0458 ,  G11C2211/565 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

摘要： A method of reading a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands. The p+ drain and the p+ source is formed in an n-well. The method comprises: applying a positive voltage to the control gate to generate a gate induced drain leakage (GIDL) current; and measuring a drain GIDL current at the drain and a source GIDL current at the source simultaneously to determine the 2-bit data stored in the memory cell.

摘要翻译： 一种读取具有p +漏极，p +源极，控制栅极和由非连接半球形硅晶粒（HSG）岛形成的浮置栅极的2位p沟道存储单元的方法。 p +漏极和p +源形成在n阱中。 该方法包括：向控制栅极施加正电压以产生栅极感应漏极泄漏（GIDL）电流; 并同时测量漏极处的漏极GIDL电流和源极上的源极GIDL电流，以确定存储在存储器单元中的2位数据。

公开(公告)号：US06255713B1

公开(公告)日：2001-07-03

申请号：US09362916

申请日：1999-07-27

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L2900

CPC分类号： H01L27/0716

摘要： A current source formed in a p-type substrate is disclose. First, a deep n-well is formed within the p-type substrate and a buried n+ layer is formed within the deep n-well. Next, a p-well is formed within the deep n-well and atop the buried n+ layer. The p-well and deep n-well are then surrounded by an isolation structure that extends from the surface of the substrate to below the level of the p-well. A n+ reference structure is formed within the p-well and a gate is formed above the p-well, the gate separated from the substrate by a thin oxide layer, the gate extending over at least a portion of the n+ reference structure. Finally, a n+ output structure is formed within the p-well. An input reference current is provided to the n+ reference structure and an output current is provided by the n+ output structure.

摘要翻译： 公开了形成在p型衬底中的电流源。 首先，在p型衬底内形成深n阱，在深n阱内形成掩埋的n +层。 接下来，在深n阱内和掩埋的n +层顶部形成p阱。 p阱和深n阱然后被从衬底的表面延伸到p阱的水平之下的隔离结构包围。 在p阱内形成n +基准结构，并在p阱的上方形成栅极，栅极通过薄氧化物层与衬底分离，栅极延伸至n +参考结构的至少一部分。 最后，在p阱内形成一个n +输出结构。 输入参考电流提供给n +参考结构，输出电流由n +输出结构提供。