公开(公告)号：US6090668A

公开(公告)日：2000-07-18

申请号：US248725

申请日：1999-02-11

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp poly tip which substantially improves the erase speed of the cell. The poly tip is formed without the need for conventional oxidation of the polysilicon floating gate. Instead, the polysilicon layer is etched using a high pressure recipe thereby forming a recess with a sloped profile into the polysilicon layer. The recess is filled with a top-oxide, which in turn serves as a hard mask in etching those portions of the polysilicon year not protected by the top-oxide layer. The edge of the polysilicon layer formed by the sloping walls of the recess forms the sharp poly tip of this invention. The sharp tip does not experience the damage caused by conventional poly oxidation processes and, therefore, provides enhanced erase speed for the split-gate flash memory cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种用于形成具有尖锐多边尖端的分裂栅极闪存单元的方法，其基本上改善了单元的擦除速度。 形成多边形，而不需要多晶硅浮动栅极的常规氧化。 相反，使用高压配方蚀刻多晶硅层，从而形成具有倾斜轮廓的凹陷到多晶硅层中。 凹部填充有顶部氧化物，其又用作蚀刻多晶硅年份未被顶部氧化物层保护的那些部分的硬掩模。 由凹陷的倾斜壁形成的多晶硅层的边缘形成本发明的尖锐的多边形尖端。 锋利的尖端不会经历由常规聚氧化过程引起的损坏，因此为分离式闪存单元提供增强的擦除速度。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US07417278B2

公开(公告)日：2008-08-26

申请号：US11122726

申请日：2005-05-05

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

摘要翻译： 提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。 这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。 接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。 控制栅极通过中间多晶硅氧化物形成在浮动栅上。 浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。 形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。 以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

公开(公告)号：US06573555B1

公开(公告)日：2003-06-03

申请号：US09587464

申请日：2000-06-05

申请人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

发明人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.

摘要翻译： 分裂门P沟道快闪存储单元以及形成分离栅极P沟道闪存单元的方法，其避免高擦除电压，编程期间的反向隧穿，漏极干扰和过度擦除问题，并且允许缩小单元尺寸。 控制门具有与侧壁相交以形成锋利边缘的凹顶表面。 通过从通道进入浮动栅极的热电子注入，用电子对浮动栅极充电来对单元进行编程。 使用Fowler-Nordheim隧道将多余的电子从浮动栅极放电到控制栅中来消除电池。 在凹顶表面和浮动栅极的相交处的尖锐边缘在控制栅极和浮动栅极之间产生高电场，以在浮动栅极和控制栅极之间仅具有适度的电压差来实现Fowler-Nordheim隧道 。 P沟道闪速存储单元对于产生热电子具有较高的冲击电离强度，使得源极和漏极结之间的距离和浮置栅极的长度可以保持较小，从而允许闪存单元的尺寸缩小 。

公开(公告)号：US06465841B1

公开(公告)日：2002-10-15

申请号：US09709589

申请日：2000-11-13

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

摘要翻译： 公开了一种形成具有形成在衬垫氧化物上的氮化物间隔物并且之前形成多晶氧化物层的分裂栅极快闪存储器单元的方法。 以这种方式，避免了在形成多晶硅氧化物之前在氮化物间隔物的蚀刻期间多晶氧化物通常会发生的任何损伤。 因此，通过反转形成间隔物和多晶氧化物的顺序，包括首先形成衬垫氧化物，也可以避免由于对下面的间隔物的不可预测的损伤而导致的多晶氧化物厚度的变化 。 结果，对于在同一晶片上以及相同或不同生产线上的不同晶片上制造的单元，都能够防止栅极间闪存单元的擦除速度的变化。

公开(公告)号：US06380583B1

公开(公告)日：2002-04-30

申请号：US09679512

申请日：2000-10-06

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

摘要翻译： 提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。 这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。 接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。 控制栅极通过中间多晶硅氧化物形成在浮动栅上。 浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。 形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。 以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

公开(公告)号：US06246075B1

公开(公告)日：2001-06-12

申请号：US09507883

申请日：2000-02-22

申请人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC分类号： H01L2358

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

摘要翻译： 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体曝光产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

公开(公告)号：US06188103B1

公开(公告)日：2001-02-13

申请号：US09196600

申请日：1998-11-20

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.

摘要翻译： 提供了一种用于形成短而尖锐的门鸟喙的方法，以便增加分闸式闪存单元的擦除速度。 这是通过在电池的第一多晶硅层中注入氮离子并将其从要形成浮栅的区域中去除来实现的。 然后，当多晶硅层被氧化形成聚氧化物时，没有氮离子的浮栅区域比仍然具有氮离子的周围区域更快地氧化。 因此，形成在多氧化物边缘的鸟嘴形状比现有技术中发现的具有更小的形状。 这导致存储单元的擦除速度的增加。

公开(公告)号：US6127227A

公开(公告)日：2000-10-03

申请号：US236491

申请日：1999-01-25

申请人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/8247

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L29/511

摘要： A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.

摘要翻译： 公开了一种形成闪存单元的方法，其中采用氮气处理或植入。 引入浮栅的多晶硅的上层的氮有助于形成包含氮 - 氧 - 硅的异常薄的层。 在生长氧化物 - 氮化物 - 氧化物的底部氧化物层（ONO）的同时，在浮动栅极和闪存单元的控制栅极之间形成栅极层，形成N-O-Si层。 第一多晶硅层中的氮提供对底部氧化物的厚度的控制，同时抑制浮动栅极中的逐渐栅极氧化（GGO）效应。 现在通过N-O-Si层增强的ONO复合材料提供增强的隔间电介质，因此提供具有更精确的耦合比和更好性能的闪存单元。

公开(公告)号：US6067254A

公开(公告)日：2000-05-23

申请号：US314590

申请日：1999-05-19

申请人： Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/10

摘要： A method of programming split gate flash memory cells which avoids erroneously programming non selected cells and allows the cell size and the array size to be shrunk below previously realizable limits. For N channel cells with the control gates connected to word lines and drains connected to bit lines a negative voltage is supplied between the non selected word lines and ground potential. For P channel cells with the control gates connected to word lines and drains connected to bit lines a positive voltage is supplied between the non selected word lines and ground potential. This allows the minimum length of the control gate over the channel region to be reduced below previously allowable limits and still prevent programming of non selected cells. This also allows cell size and array size to be reduced.

摘要翻译： 编程分裂栅极闪存单元的方法，其避免错误地编程未选择的单元，并允许单元尺寸和阵列尺寸缩小到先前可实现的极限以下。 对于具有连接到字线的控制栅极和连接到位线的漏极的N沟道单元，在非选择字线和地电位之间提供负电压。 对于具有连接到字线的控制栅极和连接到位线的漏极的P沟道单元，在非选择字线和地电位之间提供正电压。 这允许将通道区域上的控制栅极的最小长度减小到低于先前允许的极限，并且仍然阻止对未选择的单元进行编程。 这也可以减小单元格尺寸和阵列大小。

公开(公告)号：US6017795A

公开(公告)日：2000-01-25

申请号：US72996

申请日：1998-05-06

申请人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

发明人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.

摘要翻译： 提供了一种用于形成具有减小的尺寸，部分埋入的源极线，增加的源耦合比，改进的可编程性和整体增强性能的分裂栅极快闪存储器单元的方法。 分裂门电池还具有减小的尺寸和改进的性能。 源极线形成在源极区域上的衬底中的沟槽中。 沟槽壁提供增加的源耦合，并且没有门鸟的喙与沟槽一起收缩细胞尺寸。 通过浮动栅极和控制栅极之间的隔间氧化物，通过更有利的热电子注入也可以提高可编程性。