公开(公告)号：US20140281263A1

公开(公告)日：2014-09-18

申请号：US14109678

申请日：2013-12-17

Applicant: NVIDIA CORPORATION

Inventor： James Leroy DEMING ,  Jerome F. DULUK, Jr. ,  John MASHEY ,  Mark HAIRGROVE ,  Lucien DUNNING ,  Jonathon Stuart Ramsay EVANS ,  Samuel H. DUNCAN ,  Cameron BUSCHARDT ,  Brian FAHS

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F12/08 ,  G06F2212/301 ,  G06F2212/684

Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

Abstract translation: 本发明的一个实施例是包括一个或多个流式多处理器（SM）并且实现每SM的重放单元的并行处理单元（PPU）。 当检测到与由特定SM发出的存储器事务相关联的页面错误时，相应的重放单元使得SM，而不是任何未受影响的SM停止发行新的存储器事务。 重播单元然后将故障存储器事务和任何故障的飞行中存储器事务存储在重放缓冲器中。 当页面错误得到解决时，重播单元重播重播缓冲区中的内存事务，从重播缓冲区中移除成功的内存事务，直到所有存储的内存事务都已成功执行。 有利的是，与常规PPU相比，PPU的整体性能得到改善，在常规PPU检测到页面故障之后，停止执行包含在PPU中的所有SM的存储器事务，直到故障被解决为止。

公开(公告)号：US20140173258A1

公开(公告)日：2014-06-19

申请号：US13720746

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian FAHS ,  Eric T. ANDERSON ,  Nick BARROW-WILLIAMS ,  Shirish GADRE ,  Joel James MCCORMACK ,  Bryon S. NORDQUIST ,  Nirmal Raj SAXENA ,  Lacky V. SHAH

IPC: G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/3851 ,  G06F12/0284 ,  G06F12/0815 ,  G06F12/0844 ,  G06F2209/5018 ,  G06F2212/604

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Abstract translation: 可以将纹理处理流水线配置为服务于表示纹理数据访问操作或通用数据访问操作的存储器访问请求。 当纹理处理流水线接收到表示纹理数据访问操作的存储器访问请求时，纹理处理流水线可以基于纹理坐标来检索纹理数据。 当存储器访问请求表示通用数据访问操作时，纹理流水线从存储器访问请求中提取虚拟地址，然后基于虚拟地址检索数据。 纹理处理流水线还被配置为缓存代表一组线程检索的通用数据，然后在线程组退出时使该通用数据无效。

公开(公告)号：US20140123145A1

公开(公告)日：2014-05-01

申请号：US13660763

申请日：2012-10-25

Applicant: NVIDIA CORPORATION

Inventor： Nick BARROW-WILLIAMS ,  Brian FAHS ,  Jerome F. DULUK, Jr. ,  James Leroy DEMING ,  Timothy John PURCELL ,  Lucien DUNNING ,  Mark HAIRGROVE

IPC: G06F9/46

CPC classification number: G06F9/5027 ,  G06F12/1045 ,  G06F12/109

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US20140122829A1

公开(公告)日：2014-05-01

申请号：US13660815

申请日：2012-10-25

Applicant: NVIDIA CORPORATION

Inventor： Nick BARROW-WILLIAMS ,  Brian FAHS ,  Jerome F. DULUK, JR. ,  James Leroy DEMING ,  Timothy John PURCELL ,  Lucien DUNNING ,  Mark HAIRGROVE

IPC: G06F12/10

CPC classification number: G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

Abstract translation: 一种用于同时执行多个任务的技术，每个任务具有独立的虚拟地址空间，包括为每个任务分配地址空间标识符（ASID），并且构建每个虚拟存储器访问请求以包括虚拟地址和ASID。 在虚拟到物理地址转换期间，ASID选择相应的页表，其中包括ASID和相关任务的虚拟到物理地址映射。 翻译后备缓冲区（TLB）的条目包括虚拟地址和ASID，以完成对物理地址的每个映射。 可以实现对共享虚拟地址空间的任务的深度调度，以提高对TLB和数据高速缓存的高速缓存亲和性。