公开(公告)号：US20080291716A1

公开(公告)日：2008-11-27

申请号：US12123827

申请日：2008-05-20

申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

IPC分类号： G11C11/00

CPC分类号： G11C11/36

摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

公开(公告)号：US08000155B2

公开(公告)日：2011-08-16

申请号：US13005582

申请日：2011-01-13

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C7/22 ,  G11C7/06 ,  G11C11/00 ,  G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

公开(公告)号：US07983084B2

公开(公告)日：2011-07-19

申请号：US12553266

申请日：2009-09-03

申请人： Naoya Tokiwa ,  Hideo Mukai

发明人： Naoya Tokiwa ,  Hideo Mukai

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C29/028 ,  G11C2029/1202 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

摘要翻译： 本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱 其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元， 具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于 对应于地址信号的字线。

公开(公告)号：US07911854B2

公开(公告)日：2011-03-22

申请号：US12394712

申请日：2009-02-27

申请人： Hiroyuki Nagashima ,  Naoya Tokiwa

发明人： Hiroyuki Nagashima ,  Naoya Tokiwa

IPC分类号： G11C8/08

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C5/04 ,  G11C8/04 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

摘要翻译： 半导体存储器件包括多层布置的多个存储层，每个存储层包括一个单元阵列，该单元阵列包含多条第一平行线，多条第二平行线与第一条线交叉，以及多个存储器 在第一线和第二线的交叉处连接的细胞; 脉冲发生器，用于产生数据访问存储单元所需的脉冲; 以及控制装置，用于控制脉冲发生器，使得从脉冲发生器输出的脉冲具有与存取目标存储单元所属的存储层相对应的能量。

公开(公告)号：US20100097858A1

公开(公告)日：2010-04-22

申请号：US12553266

申请日：2009-09-03

申请人： Naoya Tokiwa ,  Hideo Mukai

发明人： Naoya Tokiwa ,  Hideo Mukai

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C29/028 ,  G11C2029/1202 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

摘要翻译： 本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱 其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元， 具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于 对应于地址信号的字线。

公开(公告)号：US07590006B2

公开(公告)日：2009-09-15

申请号：US11754531

申请日：2007-05-29

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C16/3436 ,  G11C16/0483

摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data storage circuit configured to store data simultaneously read from or written into the memory cell array, the data constituting a collective processing unit; and a data state judgment circuit configured to sequentially judge the data states of multiple divided areas, which are obtained by dividing the collective processing unit.

摘要翻译： 半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 数据存储电路，被配置为存储同时从存储单元阵列读取或写入存储单元阵列的数据，所述数据构成集合处理单元; 以及数据状态判断电路，被配置为顺序地判断通过分割集体处理单元获得的多个分割区域的数据状态。

公开(公告)号：US20080253192A1

公开(公告)日：2008-10-16

申请号：US12118330

申请日：2008-05-09

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C29/76 ,  G11C16/0483 ,  G11C29/82

摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement information, and a bad block information registration area with which it is possible to register bad block information. The block replacement information register group is set in accordance with the block replacement information read out of the storage unit during a boot sequence, and the bad block flag register group is set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence.

摘要翻译： 半导体集成电路装置包括具有多个块的存储单元阵列，存储单元，块替换信息寄存器组和坏块标志寄存器组。 存储单元包括可以注册块替换信息的块替换信息登记区域和可以注册坏块信息的坏块信息登记区域。 根据在引导顺序期间从存储单元读出的块替换信息来设置块替换信息寄存器组，并且根据读取的块替换信息和坏块信息两者来设置坏块标志寄存器组 在引导顺序期间从存储单元出来。

公开(公告)号：US07388782B2

公开(公告)日：2008-06-17

申请号：US11616112

申请日：2006-12-26

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C29/76 ,  G11C16/0483 ,  G11C29/82

摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement information, and a bad block information registration area with which it is possible to register bad block information. The block replacement information register group is set in accordance with the block replacement information read out of the storage unit during a boot sequence, and the bad block flag register group is set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence.

摘要翻译： 半导体集成电路装置包括具有多个块的存储单元阵列，存储单元，块替换信息寄存器组和坏块标志寄存器组。 存储单元包括可以注册块替换信息的块替换信息登记区域和可以注册坏块信息的坏块信息登记区域。 根据在引导顺序期间从存储单元读出的块替换信息来设置块替换信息寄存器组，并且根据读取的块替换信息和坏块信息两者来设置坏块标志寄存器组 在引导顺序期间从存储单元出来。

公开(公告)号：US07236424B2

公开(公告)日：2007-06-26

申请号：US11086444

申请日：2005-03-23

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C8/00 ,  G11C8/18

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元; 被配置为耦合到所述存储单元阵列的读出放大器电路; 设置在读出放大器电路和数据输入/输出端口之间的数据传输电路; 控制信号生成电路，被配置为基于外部提供的参考时钟信号生成多个控制信号，所述控制信号用于控制读出放大器电路的数据输入和输出以及数据传送电路中的数据传送定时; 以及内部时钟信号生成电路，被配置为基于用于作为控制信号的基础的参考时钟信号产生内部时钟信号，内部时钟信号具有与参考时钟信号相同的时钟周期和不具有恒定占空比的内部时钟信号 关于参考时钟信号的占空比。

公开(公告)号：US20060044874A1

公开(公告)日：2006-03-02

申请号：US11086444

申请日：2005-03-23

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元; 被配置为耦合到所述存储单元阵列的读出放大器电路; 设置在读出放大器电路和数据输入/输出端口之间的数据传输电路; 控制信号生成电路，被配置为基于外部提供的参考时钟信号生成多个控制信号，所述控制信号用于控制读出放大器电路的数据输入和输出以及数据传送电路中的数据传送定时; 以及内部时钟信号生成电路，被配置为基于用于作为控制信号的基础的参考时钟信号产生内部时钟信号，内部时钟信号具有与参考时钟信号相同的时钟周期和不具有恒定占空比的内部时钟信号 关于参考时钟信号的占空比。