公开(公告)号：US20050212023A1

公开(公告)日：2005-09-29

申请号：US11086565

申请日：2005-03-23

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L21/8247 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/112 ,  H01L27/11253

摘要： A semiconductor memory device of the invention comprises a plurality of bit lines formed by implanting a second conductive-type impurity in a first conductive-type semiconductor substrate; a thick insulating film on the bit lines; a thin insulating film between the neighboring bit lines; and a plurality of word lines formed on the thick and thin insulating films so as to cross the bit lines, wherein each of the word lines includes a plurality of first conductors and a second conductor which electrically connects the first conductors in series, the respective first conductors are formed on the thin insulating film, the top face of the thickest portion of the thick insulating film is higher than the top face of the first conductors, and the film thickness of the thick insulating film is made thinner toward the end.

摘要翻译： 本发明的半导体存储器件包括通过在第一导电型半导体衬底中注入第二导电型杂质形成的多个位线; 位线上的厚绝缘膜; 相邻位线之间的薄绝缘膜; 以及形成在厚而薄的绝缘膜上以跨越位线的多个字线，其中每个字线包括多个第一导体和将第一导体串联电连接的第二导体，第一 导体形成在薄绝缘膜上，厚绝缘膜的最厚部分的顶面高于第一导体的顶面，并且使厚绝缘膜的膜厚朝向端部变薄。

公开(公告)号：US20050180237A1

公开(公告)日：2005-08-18

申请号：US11101415

申请日：2005-04-08

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G11C16/02 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/3427 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3418

摘要： A method of writing data into a non-volatile semiconductor memory having a plurality of memory cells in which a word line is shared by memory cells and a bit line is shared by adjacent memory cells, the method including writing the data into memory cells connected to the same word line sequentially from a memory cell at one end to a memory cell at another end.

公开(公告)号：US06894913B2

公开(公告)日：2005-05-17

申请号：US10315095

申请日：2002-12-10

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G11C16/02 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C5/02

CPC分类号： G11C16/3427 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3418

摘要： A method of writing data into a non-volatile semiconductor memory having a plurality of memory cells in which a word line is shared by memory cells and a bit line is shared by adjacent memory cells, the method including writing the data into memory cells connected to the same word line sequentially from a memory cell at one end to a memory cell at another end.

摘要翻译： 一种将数据写入非易失性半导体存储器的方法，所述非易失性半导体存储器具有多个存储器单元，其中字线由存储器单元共享并且位线由相邻存储器单元共享，所述方法包括将数据写入连接到 相同的字线顺序地从一端的存储器单元到另一端的存储器单元。

公开(公告)号：US6101128A

公开(公告)日：2000-08-08

申请号：US198392

申请日：1998-11-24

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115

摘要： The nonvolatile semiconductor memory of this invention includes: a semiconductor substrate; a plurality of memory cells formed in a matrix on the semiconductor substrate, each of the memory cells including a first insulating film formed on the semiconductor substrate, a floating gate formed on the first insulating film, and a control gate formed on the floating gate via a second insulating film sandwiched therebetween, a source diffusion region, and a drain diffusion region; a diffusion layer formed in a portion of the semiconductor substrate located between two of the memory cells adjacent in a first direction, the diffusion layer including the drain diffusion region for one of the two memory cells and the source diffusion region for the other memory cell; a word line formed by connecting the control gates of the memory cells lined in the first direction; and a bit line formed by connecting the diffusion layers lined in a second direction substantially perpendicular to the first direction, wherein the memory cells have a structure in which a tunnel current flows between the drain diffusion region and the floating gate of one of the two adjacent memory cells via the first insulating film when a predetermined voltage is applied to the diffusion layer and no tunnel current flows between the diffusion layer and the floating gate of the other memory cell.

摘要翻译： 本发明的非易失性半导体存储器包括：半导体衬底; 在半导体衬底上形成矩阵的多个存储单元，每个存储单元包括形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的浮置栅极和形成在浮动栅极上的控制栅极 夹在其间的第二绝缘膜，源极扩散区和漏极扩散区; 位于两个与第一方向相邻的两个存储单元之间的半导体衬底的一部分中的扩散层，包括用于两个存储单元之一的漏极扩散区域的扩散层和用于另一个存储单元的源极扩散区域; 通过连接沿第一方向排列的存储单元的控制栅极形成的字线; 以及通过连接沿基本上垂直于第一方向的第二方向排列的扩散层形成的位线，其中存储单元具有其中隧道电流在两个相邻的一个之一的漏极扩散区域和浮置栅极之间流动的结构 当向扩散层施加预定电压并且在扩散层和另一个存储单元的浮置栅极之间没有隧道电流流动时，经由第一绝缘膜的存储单元。

公开(公告)号：US5424232A

公开(公告)日：1995-06-13

申请号：US806296

申请日：1991-12-13

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L27/115 ,  H01L29/42324 ,  Y10S438/981

摘要： A non-volatile memory having a Floating Gate Oxide type field effect transistor provided with a floating gate on a semiconductor substrate through a tunnel oxide film, including an oxide blocking film formed on the side wall of the floating gate for preventing a tunnel insulating film from being thermally oxidized by thermal oxidation.

摘要翻译： 一种具有浮栅型氧化物型场效应晶体管的非易失性存储器，其通过隧道氧化膜在半导体衬底上设置有浮置栅极，该沟道氧化物膜包括形成在浮置栅极的侧壁上的氧化物阻挡膜，用于防止隧道绝缘膜 被热氧化热氧化。

公开(公告)号：US5414286A

公开(公告)日：1995-05-09

申请号：US33560

申请日：1993-03-18

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/68

CPC分类号： H01L27/115 ,  G11C16/0433

摘要： A nonvolatile memory including a plurality of memory cells comprising a semiconductor substrate, a first electrode formed on the substrate, a floating gate formed on the side wall of the first electrode, and a second electrode, wherein the memory cells are arranged in X and Y directions to form a matrix; the first electrodes of memory cells arranged in the Y direction are connected in common in the Y direction, the second electrodes are connected in common in the Y direction; a memory cell and one of its adjacent memory cells arranged in the X direction have a first impurity diffused layer in common; the memory cell and the other adjacent memory thereof have a second impurity diffused layer in common; and the first impurity diffused layers of the memory cells arranged in the X direction are further connected in common by a conductive layer.

摘要翻译： 一种包括多个存储单元的非易失性存储器，包括半导体衬底，形成在衬底上的第一电极，形成在第一电极的侧壁上的浮动栅极和第二电极，其中存储单元布置在X和Y中 形成矩阵的方向; 沿Y方向排列的存储单元的第一电极在Y方向上共同连接，第二电极在Y方向上共同连接; 在X方向排列的存储单元及其相邻存储单元之一具有共同的第一杂质扩散层; 存储单元和其它相邻的存储器具有共同的第二杂质扩散层; 并且沿X方向布置的存储单元的第一杂质扩散层通过导电层进一步连接。

公开(公告)号：US5251171A

公开(公告)日：1993-10-05

申请号：US644332

申请日：1991-01-18

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L21/8247 ,  G11C11/00 ,  G11C14/00 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C11/005 ,  G11C14/00 ,  Y10S257/908

摘要： A method which can operate a semiconductor memory device having a volatile memory and a non-volatile memory without lowering the retention characteristic of the non-volatile memory is described. The volatile memory includes a MOS transistor, and a capacitor, one electrode of which is connected to the source of the MOS transistor. The non-volatile memory includes a floating gate transistor. The semiconductor memory device further has a switch connected between the source of the MOS transistor and the drain of the floating gate transistor. The control gate of the floating gate transistor is connected to the source of the MOS transistor. When the switch is off and the volatile memory to be operated, a voltage which is substantially one half of that of a power source voltage with respect to the ground level is applied to the source of the floating gate transistor.

摘要翻译： 描述了可以操作具有易失性存储器和非易失性存储器而不降低非易失性存储器的保持特性的半导体存储器件的方法。 易失性存储器包括MOS晶体管和电容器，其一个电极连接到MOS晶体管的源极。 非易失性存储器包括浮栅晶体管。 半导体存储器件还具有连接在MOS晶体管的源极和浮置栅极晶体管的漏极之间的开关。 浮栅晶体管的控制栅极连接到MOS晶体管的源极。 当开关关闭并且易于操作的易失性存储器时，相对于地电平的电源电压的电压基本上是一半的电压被施加到浮栅晶体管的源极。

公开(公告)号：US5172199A

公开(公告)日：1992-12-15

申请号：US711056

申请日：1991-06-06

申请人： Yoshimitsu Yamauchi ,  Kenichi Tanaka ,  Keizo Sakiyama

发明人： Yoshimitsu Yamauchi ,  Kenichi Tanaka ,  Keizo Sakiyama

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L29/42324 ,  H01L27/115

摘要： A nonvolatile semiconductor memory device including a semiconductor substrate, a pair of impurity diffusion regions provided in the substrate, a gate region provided between the pair of impurity diffusion regions, a first gate electrode stacked on the gate region via a first dielectric film, and a second gate electrode stacked on the first gate electrode via a second dielectric film, the first gate electrode being electrically short-circuited to one of the impurity diffusion regions.

摘要翻译： 一种非易失性半导体存储器件，包括半导体衬底，设置在衬底中的一对杂质扩散区，设置在该对杂质扩散区之间的栅极区，经由第一绝缘膜堆叠在栅极区上的第一栅电极， 第二栅电极经由第二电介质膜堆叠在第一栅电极上，第一栅电极与一个杂质扩散区电短路。

公开(公告)号：US5065201A

公开(公告)日：1991-11-12

申请号：US488874

申请日：1990-03-06

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L21/8247 ,  G11C14/00 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L29/7883

摘要： A semiconductor device includes a DRAM section constituting one MOS transistor and one capacitor, and an EEPROM section constituting one FLOTOX MOS transistor. A control gate electrode of the FLOTOX MOS transistor is connected to a source area of the MOS transistor of the DRAM section, on which is placed a capacitor electrode through an insulation layer, so that the control gate is made a storage node of the DRAM section. Thus, a combination of EEPROM cell and DRAM cell provides a NVRAM cell. When a data change is desired, the NVRAM cell works as DRAM. On the other hand, when data is to be preserved for a longer time, the data is transferred from DRAM section to EEPROM section by the NVRAM cell to be stored in EEPROM section. Since the capacitor of DRAM section has its storage node in common with a control gate of EEPROM section, the number of elements per cell can be reduced, thereby satisfying the requirement for applications of NVRAM cell to high density devices.

摘要翻译： 半导体器件包括构成一个MOS晶体管和一个电容器的DRAM部分和构成一个FLOTOXMOS晶体管的EEPROM部分。 FLOTOXMOS晶体管的控制栅电极连接到DRAM部分的MOS晶体管的源极区域，其中通过绝缘层放置电容器电极，使得控制栅极成为DRAM部分的存储节点 。 因此，EEPROM单元和DRAM单元的组合提供NVRAM单元。 当需要数据更改时，NVRAM单元作为DRAM工作。 另一方面，当数据要保存较长时间时，数据由NVRAM单元从DRAM部分传送到EEPROM部分，以存储在EEPROM部分。 由于DRAM部分的电容器具有与EEPROM部分的控制栅极共同的存储节点，因此可以减少每个单元的元件数量，从而满足NVRAM单元对高密度器件的应用的需求。

公开(公告)号：US08947418B2

公开(公告)日：2015-02-03

申请号：US13989492

申请日：2011-10-05

申请人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3618 ,  G09G3/3648 ,  G09G2300/0876 ,  G09G2300/088 ,  G09G2310/08

摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.

摘要翻译： 提供了一种在不降低开口率的情况下实现低功耗的显示装置。 液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端 形成内部节点N1。 第一开关电路22和第二开关电路23的其他端子连接到源极线SL。 第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。 第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。 升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。 二极管D1具有从源极线SL到内部节点N1的整流功能。