公开(公告)号：US20200176395A1

公开(公告)日：2020-06-04

申请号：US16780921

申请日：2020-02-04

申请人： Powertech Technology Inc.

发明人： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

IPC分类号： H01L23/552 ,  H01L25/065 ,  H01L23/00

摘要： A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

公开(公告)号：US10607860B2

公开(公告)日：2020-03-31

申请号：US15713708

申请日：2017-09-25

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

IPC分类号： H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L21/683

摘要： A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.

公开(公告)号：US10593629B2

公开(公告)日：2020-03-17

申请号：US16030826

申请日：2018-07-09

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chiang ,  Li-Chih Fang ,  Wen-Jeng Fan

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/367 ,  H01L23/552 ,  H01L21/683 ,  H01L23/13

摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.

公开(公告)号：US20190096699A1

公开(公告)日：2019-03-28

申请号：US15713708

申请日：2017-09-25

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

IPC分类号： H01L21/56 ,  H01L21/48 ,  H01L21/78

摘要： A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.

公开(公告)号：US09825010B2

公开(公告)日：2017-11-21

申请号：US15455143

申请日：2017-03-10

申请人： Powertech Technology Inc.

发明人： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/552

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82039 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/15192 ,  H01L2924/3025

摘要： A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

公开(公告)号：US09659911B1

公开(公告)日：2017-05-23

申请号：US15264606

申请日：2016-09-14

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Li-Chih Fang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer (RDL), at least one first die, a plurality of conductive terminals and solder balls, a first encapsulant, a plurality of second dies, and a second encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first die and the conductive terminals are electrically connected to the RDL and are located on the first surface of the RDL. The first encapsulant encapsulates the first die and the conductive terminals. The first encapsulant exposes part of the conductive terminals. The solder balls are electrically connected to the conductive terminals and are located over the conductive terminals exposed by the first encapsulant. The second dies are electrically connected to the RDL and are located on the second surface of the RDL. The second encapsulant encapsulates the second dies.