公开(公告)号：US10128211B2

公开(公告)日：2018-11-13

申请号：US15630940

申请日：2017-06-22

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Yong-Cheng Chuang ,  Yu-Tso Lin

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L23/16 ,  H01L21/56

摘要： A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

公开(公告)号：US20180211936A1

公开(公告)日：2018-07-26

申请号：US15630940

申请日：2017-06-22

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Yong-Cheng Chuang ,  Yu-Tso Lin

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511

摘要： A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

公开(公告)号：US20190189494A1

公开(公告)日：2019-06-20

申请号：US15847936

申请日：2017-12-20

申请人： Powertech Technology Inc.

发明人： Hsing-Te Chung ,  Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Nan-Chun Lin

IPC分类号： H01L21/683 ,  H01L23/498 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L21/6835 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68309 ,  H01L2221/68368 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/19105 ,  H01L2924/19106

摘要： A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.

公开(公告)号：US20180138149A1

公开(公告)日：2018-05-17

申请号：US15353721

申请日：2016-11-16

申请人： Powertech Technology Inc.

发明人： Chien-Wei Chou ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H05K1/18 ,  H05K1/11 ,  H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H05K1/02

CPC分类号： H01L25/0657 ,  H01L21/4821 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/181 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2924/014

摘要： A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. The dummy pads surround the signal pads. The bottom package structure is disposed over the circuit board. The bottom package structure is electrically connected to the signal pads. The top package structure is disposed over the bottom package structure. The top package structure is electrically connected to the bottom package structure. The metal frame structure includes a body and a plurality of terminal pins. The body is located between the top package structure and the bottom package structure. The terminal pins extend outward from an edge of the top package structure to connect the top package structure and the dummy pads of the circuit board.

公开(公告)号：US20170309597A1

公开(公告)日：2017-10-26

申请号：US15491982

申请日：2017-04-20

申请人： Powertech Technology Inc.

发明人： Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Li-Chih Fang ,  Chia-Jen Chou

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

公开(公告)号：US09673178B2

公开(公告)日：2017-06-06

申请号：US14970558

申请日：2015-12-16

申请人： Powertech Technology Inc.

发明人： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

摘要： Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US20170110439A1

公开(公告)日：2017-04-20

申请号：US14970558

申请日：2015-12-16

申请人： Powertech Technology Inc.

发明人： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

摘要： Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US10304716B1

公开(公告)日：2019-05-28

申请号：US15847936

申请日：2017-12-20

申请人： Powertech Technology Inc.

发明人： Hsing-Te Chung ,  Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Nan-Chun Lin

IPC分类号： H01L21/683 ,  H01L23/498 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L21/6835 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68309 ,  H01L2221/68368 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/19105 ,  H01L2924/19106

摘要： A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.

公开(公告)号：US09859187B2

公开(公告)日：2018-01-02

申请号：US15385320

申请日：2016-12-20

申请人： POWERTECH TECHNOLOGY INC.

发明人： Yong-Cheng Chuang

IPC分类号： H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/3675 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/17132 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/351 ,  H01L2924/3512

摘要： Disclosed is a BGA package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of BGA packages. A chip is disposed on the upper surface of the substrate. A chip projective area is defined inside the bottom surface of the substrate and is established by vertically projecting the edges of the chip on the upper surface to the bottom surface of the substrate. At least an external contact pad vulnerable to thermal stress is located within the chip projective area. A protective area and a wiring area are respectively defined in the chip projective area at two opposing sides of the external contact pad. A plurality of protective mini-pads are arranged in a dotted-line layout and disposed in the projective area to partially surround the external contact pad to avoid thermal stress concentrated on the protective area and to further prevent circuitry cracks in the package structure.

公开(公告)号：US09659911B1

公开(公告)日：2017-05-23

申请号：US15264606

申请日：2016-09-14

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Li-Chih Fang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer (RDL), at least one first die, a plurality of conductive terminals and solder balls, a first encapsulant, a plurality of second dies, and a second encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first die and the conductive terminals are electrically connected to the RDL and are located on the first surface of the RDL. The first encapsulant encapsulates the first die and the conductive terminals. The first encapsulant exposes part of the conductive terminals. The solder balls are electrically connected to the conductive terminals and are located over the conductive terminals exposed by the first encapsulant. The second dies are electrically connected to the RDL and are located on the second surface of the RDL. The second encapsulant encapsulates the second dies.