-
21.发明申请公开(公告)号：US20070128526A1
公开(公告)日：2007-06-07
申请号：US11297209
申请日：2005-12-07
CPC分类号： G03F1/36
摘要： Sub-resolution assist features for non-collinear features are described for use in photolithography. A photolithography mask with elongated features is synthesized. An end-to-end gap between two features if found for which the ends of the two features facing the gap are linearly offset from one another. A sub-resolution assist feature is applied to the end-to-end gap between the elongated features, and the synthesized photolithography mask is modified to include the sub-resolution assist feature.
摘要翻译： 描述了非共线特征的子分辨率辅助功能，用于光刻。 合成具有细长特征的光刻掩模。 如果发现两个特征面对间隙的两端的端部彼此线性偏移，则两个特征之间的端对端间隙。 子分辨率辅助特征被应用于细长特征之间的端到端间隙，并且合成的光刻掩模被修改为包括子分辨率辅助特征。
-
22.发明申请公开(公告)号：US20050148180A1
公开(公告)日：2005-07-07
申请号：US10750200
申请日：2003-12-30
申请人： Swaminathan Sivakumar , Curtis Ward , Timothy Hehr , Mark Fradkin
发明人： Swaminathan Sivakumar , Curtis Ward , Timothy Hehr , Mark Fradkin
IPC分类号： H01L21/033 , H01L21/302 , H01L21/311 , H01L21/461 , H01L21/768 , H01L23/04 , H01L23/485
CPC分类号： H01L21/76804 , H01L21/0335 , H01L21/31144 , H01L24/05 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： The present invention relates to exposing a bond pad on a substrate. A bond pad is formed over a silicon substrate with the subsequent formation of a dielectric over the bond pad. A patterned resist is formed, and at least opening is processed to form a sloped sidewall profile. The sloped sidewall profile is subsequently etched and transferred to the dielectric layer, exposing the bond pad.
-
23.发明授权公开(公告)号：US10211088B2
公开(公告)日：2019-02-19
申请号：US15743616
申请日：2015-09-10
IPC分类号： H01L21/768 , H01L23/522 , H01L21/311 , H01L23/528 , H01L21/033
摘要： Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
-
公开(公告)号：US08233210B2
公开(公告)日：2012-07-31
申请号：US12319014
申请日：2008-12-30
CPC分类号： G03B27/72 , G03F7/701 , G03F7/70191
摘要： Embodiments of systems and methods for providing a hybrid illumination aperture in optical lithography are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文中通常描述用于在光学光刻中提供混合照明孔径的系统和方法的实施例。 可以描述和要求保护其他实施例。
-
25.发明授权Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby 有权在挖掘特征的垂直侧壁上图案化金属的方法，使用其形成嵌入式MIM电容器的方法以及由此产生的嵌入式存储器件公开(公告)号：US07927959B2
公开(公告)日：2011-04-19
申请号：US12286338
申请日：2008-09-30
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L21/467
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译： 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。
-
公开(公告)号：US20100062228A1
公开(公告)日：2010-03-11
申请号：US12205744
申请日：2008-09-05
CPC分类号： G03F7/0035 , Y10T428/24802
摘要： A method of forming a pattern on a wafer is provided. The method includes applying a photoresist on the wafer and exposing the wafer to define a first pattern on the photoresist. The method also includes exposing the wafer to define a second pattern on the photoresist, wherein each of the first and second patterns comprises unexposed portions of the photoresist and developing the wafer to form the first and second patterns on the photoresist, wherein the first and second patterns are formed by removing the unexposed portions of the photoresist.
摘要翻译： 提供了在晶片上形成图案的方法。 该方法包括在晶片上施加光致抗蚀剂并暴露晶片以在光致抗蚀剂上限定第一图案。 该方法还包括曝光晶片以限定光致抗蚀剂上的第二图案，其中第一和第二图案中的每一个包括光致抗蚀剂的未曝光部分，并且显影晶片以在光致抗蚀剂上形成第一和第二图案，其中第一和第二图案 通过去除光致抗蚀剂的未曝光部分形成图案。
-
公开(公告)号：US20090263751A1
公开(公告)日：2009-10-22
申请号：US12148826
申请日：2008-04-22
IPC分类号： G03F7/38
CPC分类号： G03F7/38 , G03F7/405 , H01L21/0274
摘要： Embodiments of methods for double patterning photoresist are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述用于双重图案化光刻胶的方法的实施例。 可以描述和要求保护其他实施例。
-
公开(公告)号：US20080318137A1
公开(公告)日：2008-12-25
申请号：US11820420
申请日：2007-06-19
IPC分类号： G03F1/00
摘要： In one embodiment, a mask for use in semiconductor processing comprises a first region formed from a first material that is primarily opaque, a second region formed from a second material that is primarily transmissive, and a third region in which at least a portion of the second material is removed to generate a phase shift in radiation applied to the mask.
摘要翻译： 在一个实施例中，用于半导体处理的掩模包括由主要是不透明的第一材料形成的第一区域，由主要透射的第二材料形成的第二区域，以及第三区域，其中至少一部分 第二材料被去除以产生施加到掩模的辐射的相移。
-
29.发明授权公开(公告)号：US07358111B2
公开(公告)日：2008-04-15
申请号：US11262247
申请日：2005-10-28
IPC分类号： H01L21/00
CPC分类号： G03F7/095 , G03F7/091 , H01L21/0276
摘要： A semiconductor wafer may be coated with an imageable anti-reflective coating. As a result, the coating may be removed using the same techniques used to remove overlying photoresists. This may overcome the difficulty of etching anti-reflective coatings using standard etches because of their poor selectivity to photoresist and the resulting propensity to cause integrated circuit defects arising from anti-reflective coating remnants.
摘要翻译： 可以用可成像的抗反射涂层涂覆半导体晶片。 结果，可以使用用于去除覆盖的光致抗蚀剂的相同技术去除涂层。 这可以克服使用标准蚀刻来蚀刻抗反射涂层的难度，因为它们对光致抗蚀剂的选择性差，并导致由抗反射涂层残留物引起集成电路缺陷的倾向。
-
30.发明授权Solvent vapor-assisted plasticization of photoresist films to achieve critical dimension reduction during temperature reflow 失效溶剂气相辅助增塑光致抗蚀剂膜，以在温度回流过程中实现临界尺寸降低公开(公告)号：US06977219B2
公开(公告)日：2005-12-20
申请号：US10749739
申请日：2003-12-30
IPC分类号： G03F7/40 , H01L21/027 , H01L21/033 , H01L21/311 , H01L21/4763 , H01L21/768
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/0338 , H01L21/31144 , H01L21/76802
摘要： The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The post exposure and developed resist pattern is exposed to a solvent prior to a bake or reflow process. Exposure to the solvent lowers the molecular weight of the resist material, modifying the resist material's reflow rate. The post-exposure resist is then easier to control during a subsequent reflow process to reduce the hole or line size of the patterned resist.
摘要翻译： 本发明涉及减小制造集成电路中的关键尺寸和减小特征尺寸。 具体地说，该方法控制光致抗蚀剂的流速，以发展超出所使用的光致抗蚀剂材料的分辨率极限以及光刻工具组的极限的关键尺寸。 在烘烤或回流处理之前，将后曝光和显影的抗蚀剂图案暴露于溶剂。 暴露于溶剂会降低抗蚀剂材料的分子量，改变抗蚀材料的回流速率。 在后续回流过程中，后曝光抗蚀剂更容易控制，以减小图案化抗蚀剂的孔或线尺寸。
-
-
-
-
-
-
-
-
-
搜索结果
65 条记录 (耗时 0.031 秒)
