公开(公告)号：US20090162978A1

公开(公告)日：2009-06-25

申请号：US12395506

申请日：2009-02-27

Applicant: Vladislav Vashchenko ,  Peter J. Hopper

Inventor： Vladislav Vashchenko ,  Peter J. Hopper

IPC: H01L21/332

CPC classification number: H01L27/0259

Abstract: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.

Abstract translation: 用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。 通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。

公开(公告)号：US07479435B1

公开(公告)日：2009-01-20

申请号：US11007565

申请日：2004-12-08

Applicant: Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

Inventor： Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

IPC: H01L29/788

CPC classification number: H01L21/26586 ,  H01L21/2652 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847

Abstract: A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.

Abstract translation: 可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。 在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。 可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。

公开(公告)号：US07394133B1

公开(公告)日：2008-07-01

申请号：US11216774

申请日：2005-08-31

Applicant: Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

Inventor： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

IPC: H01L29/72

CPC classification number: H01L27/0262 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/87

Abstract: In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.

Abstract translation: 在ESD保护结构中，通过在NMOS器件周围形成n阱隔离环来提供双向ESD保护，使得形成NMOS漏极的p阱通过n阱与下面的p衬底隔离 隔离环。 通过形成n阱隔离环，提供了用于反向ESD保护的嵌入式SCR的p-n-p-n结构。 调整n阱隔离环的宽度及其与NMOS漏极的间隔，以提供所需的SCR参数。

公开(公告)号：US07250842B1

公开(公告)日：2007-07-31

申请号：US11200384

申请日：2005-08-09

Applicant: Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

Inventor： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

IPC: H01F5/00

CPC classification number: H01F41/046 ,  H01F10/14 ,  H01F10/265 ,  H01F17/0033 ,  H01F41/309 ,  H01F2017/0066

Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.

Abstract translation: 通过利用在磁芯结构周围形成的单个厚的宽的环形环来形成提供单位毫欧范围电阻的非常非常低的电阻微机电系统（MEMS）电感器。 磁芯结构又可以利用具有易轴和硬轴的叠层Ni-Fe结构。

公开(公告)号：US07233521B1

公开(公告)日：2007-06-19

申请号：US11078761

申请日：2005-03-11

Applicant: Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashshenco ,  Philipp Lindorfer

Inventor： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashshenco ,  Philipp Lindorfer

IPC: G11C11/34

CPC classification number: G11C27/005 ,  G11C11/5621 ,  G11C16/0441 ,  G11C16/10

Abstract: A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.

Abstract translation: 一种能够接收模拟信号并将其存储为数字信号的存储装置。 存储装置包括被配置为接收模拟输入电压的输入节点和两个非易失性存储单元。 第二非易失性存储单元被耦合以从输入节点接收模拟输入信号。 第二非易失性存储单元能够被编程为多个编程状态之一。 耦合到第二非易失性存储单元的第一非易失性存储单元也能够被编程为多个编程状态之一。 在操作期间，第二非易失性存储器单元和第一非易失性存储器单元都被编程为指示模拟输入电压的大小的选择的第二编程状态。 第一编程状态和第二编程状态一起表示与模拟输入电压的大小相称的数字值。

公开(公告)号：US07218555B2

公开(公告)日：2007-05-15

申请号：US11242094

申请日：2005-10-03

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

IPC: G11C11/34 ,  H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/14603 ,  H01L27/14609

Abstract: The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

Abstract translation: 成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。 光能从EPROM结构的沟道区形成光电子。 光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。

公开(公告)号：US07209503B1

公开(公告)日：2007-04-24

申请号：US10838671

申请日：2004-05-03

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC: H01S5/00

CPC classification number: H01L27/1446 ,  H01L27/146

Abstract: An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.

Abstract translation: 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。

公开(公告)号：US07113427B1

公开(公告)日：2006-09-26

申请号：US11076711

申请日：2005-03-09

Applicant: Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

Inventor： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7881

Abstract: NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.

Abstract translation: 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。

公开(公告)号：US07075341B1

公开(公告)日：2006-07-11

申请号：US10823455

申请日：2004-04-13

Applicant: Vladislav Vashchenko ,  Yuri Mirgorodski ,  Peter J. Hopper

Inventor： Vladislav Vashchenko ,  Yuri Mirgorodski ,  Peter J. Hopper

IPC: H03B1/00

CPC classification number: H01L27/0266

Abstract: A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.

Abstract translation: 提供消耗片上低空间的线性时间驱动电路。 时间驱动电路基于5V容限级联NMOS器件，单栅极器件和齐纳二极管的合并区域的小电容器电荷。

公开(公告)号：US07057174B1

公开(公告)日：2006-06-06

申请号：US10355904

申请日：2003-01-30

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Michael Mian

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Michael Mian

IPC: H01L31/00

CPC classification number: H01L31/08

Abstract: A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed adjacent to the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in the magnetic flux.

Abstract translation: 能够检测千兆赫兹光信号的光子检测器利用与电感线圈相邻形成的光子材料层。 当脉冲光源被施加到光子材料层时，光子材料产生改变电感器的磁通量的涡流。 然后可以通过检测磁通量的变化来检测信号。