Hybrid Impedance Compensation in a Buffer Circuit
    21.
    发明申请
    Hybrid Impedance Compensation in a Buffer Circuit 有权
    缓冲电路中的混合阻抗补偿

    公开(公告)号:US20120326768A1

    公开(公告)日:2012-12-27

    申请号:US13165195

    申请日:2011-06-21

    CPC classification number: H03F3/3022 H03F1/308 H03F1/56 H03F2200/447

    Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

    Abstract translation: 用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。 监视器电路包括上拉部分,其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。 监视器电路被配置为跟踪缓冲电路的输出级的操作,并且可操作地产生至少第一控制信号,该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态 缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。 控制电路用于产生作为第一控制信号的函数的一组数字控制位。 该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

    VACUUM PANEL WITH BALANCED VACUUM AND PRESSURE RESPONSE
    22.
    发明申请
    VACUUM PANEL WITH BALANCED VACUUM AND PRESSURE RESPONSE 有权
    具有平衡真空和压力响应的真空面板

    公开(公告)号:US20120205341A1

    公开(公告)日:2012-08-16

    申请号:US13028244

    申请日:2011-02-16

    CPC classification number: B65D1/42 B65D1/0223 B65D23/102 B65D79/005

    Abstract: A container comprising a finish, a sidewall portion extending from the finish, a base portion extending from the sidewall portion and enclosing the sidewall portion to form a volume therein for retaining a commodity, and a panel area disposed in the sidewall portion. The panel area having a belt land portion and a pair of inset portions in mirrored arrangement relative to the belt land portion.

    Abstract translation: 一种容器,其特征在于,包括一个整理剂,一个侧面部分,从顶部延伸出来;一个基部,从该侧壁部分延伸并包围该侧壁部分,以便在其中形成用于保持一个商品的容积;以及一个设置在侧壁部分中的面板区域。 所述面板区域具有皮带接合部分和相对于所述皮带接合部分以镜面布置的一对插入部分。

    POINT-TO-MULTIPOINT CONNECTIONS FOR DATA DELIVERY
    23.
    发明申请
    POINT-TO-MULTIPOINT CONNECTIONS FOR DATA DELIVERY 有权
    数据传输的点对多点连接

    公开(公告)号:US20110170543A1

    公开(公告)日:2011-07-14

    申请号:US13053658

    申请日:2011-03-22

    CPC classification number: H04L12/1881 H04L12/1854 H04L67/28 H04L67/2861

    Abstract: A method, device and non-transitory computer-readable storage medium transferring information using a network. The information transferred by connecting a destination device operatively to a storage device using the network. The storage device storing information to be transmitted to the destination device. The network providing a point-to-multipoint connection between an origin device and a plurality of destination devices. The plurality of destination devices including the destination device. Also, the information being transferred by receiving the information stored in the storage device by the destination device in response to the destination device being operatively connected to the storage device. The information received by the destination device having been transmitted from the origin device to the network prior to the destination device being operatively connected to the storage device.

    Abstract translation: 一种使用网络传送信息的方法,设备和非暂时计算机可读存储介质。 通过使用网络将目的地设备可操作地连接到存储设备而传送的信息。 存储装置存储要发送到目的地装置的信息。 网络提供源设备和多个目的设备之间的点对多点连接。 多个目的地设备包括目的地设备。 此外,响应于目的地设备可操作地连接到存储设备,通过由目的地设备接收存储在存储设备中的信息来传送信息。 在目的地设备被操作地连接到存储设备之前,目的地设备已经从原始设备发送到网络的信息。

    Apparatus and method for employing cloning for software development
    24.
    发明申请
    Apparatus and method for employing cloning for software development 审中-公开
    使用克隆进行软件开发的装置和方法

    公开(公告)号:US20060200645A1

    公开(公告)日:2006-09-07

    申请号:US11073784

    申请日:2005-03-07

    Applicant: Pankaj Kumar

    Inventor: Pankaj Kumar

    CPC classification number: G06F8/36

    Abstract: The present invention provides a method and apparatus for employing cloning for creating hierarchies of artifacts needed for development of software. The present invention also applies to managing cloning for the maintenance and modification of software artifacts including tracking and propagating the changes to the artifacts. In accordance with the present invention, cloning is applied to create new artifacts.

    Abstract translation: 本发明提供了一种用于使用克隆来创建开发软件所需的伪像层次的方法和装置。 本发明还适用于管理用于维护和修改软件工件的克隆,包括跟踪和传播对工件的改变。 根据本发明,应用克隆来创建新的伪像。

    Processing out of order transactions for mirrored subsystems using a cache to track write operations
    28.
    发明授权
    Processing out of order transactions for mirrored subsystems using a cache to track write operations 有权
    处理使用高速缓存跟踪写入操作的镜像子系统的顺序事务

    公开(公告)号:US08909862B2

    公开(公告)日:2014-12-09

    申请号:US12495676

    申请日:2009-06-30

    CPC classification number: G06F11/1666 G06F11/20 G06F2201/82

    Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems. A first device (that is mirroring data from a second device) includes a cache to track out of order write operations prior to writing data from the write operations to memory. A register may be used to track the state of the cache in response to receipt of a special transaction, which may be a posted transaction or snapshot. The first devise transmits an acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Devices may communicate via a peripheral component interconnect express (PCIe) interconnect, and may include a point-to-point or serial link. Various components may be on the same integrated circuit die. An uninterrupted power supply or batteries may supply power in response to a power failure.

    Abstract translation: 涉及处理镜像子系统的乱序事务的方法和装置。 第一设备(即来自第二设备的镜像数据)包括在从写入操作到存储器的数据写入之前跟踪故障写入操作的高速缓存。 可以使用寄存器来跟踪高速缓存的状态以响应特殊事务的接收,这可以是已发布的事务或快照。 一旦在寄存器的选择点处记录的所有缓存条目被清空或以其他方式被无效,则第一设备将数据承诺的确认传送到存储器。 设备可以通过外围组件互连快速(PCIe)互连进行通信,并且可以包括点到点或串行链路。 各种组件可以在相同的集成电路管芯上。 不间断的电源或电池可能会供电以响应电源故障。

    Impedance mismatch detection circuit
    29.
    发明授权
    Impedance mismatch detection circuit 有权
    阻抗失配检测电路

    公开(公告)号:US08803535B2

    公开(公告)日:2014-08-12

    申请号:US13171725

    申请日:2011-06-29

    CPC classification number: H03F3/45475 H03F2203/45594

    Abstract: A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.

    Abstract translation: 用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器,用于接收第一和第二信号,并产生一个第三信号,该第三信号指示第一和第二信号之间的差值 和第二信号。 第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号,该下拉电流被缩放规定量。 参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。 下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。 与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压,该参考电压限定与待监视电路相关联的规定阻抗失配阈值。

    Engine catalyst diagnostics
    30.
    发明授权
    Engine catalyst diagnostics 有权
    发动机催化剂诊断

    公开(公告)号:US08800356B2

    公开(公告)日:2014-08-12

    申请号:US13247640

    申请日:2011-09-28

    Abstract: Embodiments for predicting catalyst function are disclosed. One example embodiment includes applying a set of parameter readings for a given sample to a support vector machine to generate a classification output, recording a plurality of classification outputs for a plurality of successive samples over a first duration, and indicating catalyst degradation if a threshold percentage of the classification outputs indicates degraded catalyst performance. In this way, catalyst degradation may be indicated using a simplified model that does not require extensive calibration.

    Abstract translation: 公开了用于预测催化剂功能的实施方案。 一个示例性实施例包括将给定样本的一组参数读数应用于支持向量机以产生分类输出,在第一持续时间内记录多个连续样本的多个分类输出,并且如果阈值百分比 的分类输出表明催化剂性能下降。 以这种方式,可以使用不需要大量校准的简化模型来指示催化剂降解。

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