公开(公告)号：US20170118039A1

公开(公告)日：2017-04-27

申请号：US15299260

申请日：2016-10-20

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04L12/40

CPC classification number: H04L12/40136 ,  G06F13/42 ,  H04L12/40032 ,  H04L12/40039 ,  Y02D50/20

Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. A method includes receiving a first code word transmitted while a physical interface of the device is configured to operate in a low-power mode of operation, reconfiguring the physical interface in response to the first code word such that it operates in a high-speed mode, transmitting data while the physical interface operates in the high-speed mode of operation, receiving a second code word transmitted while the physical interface operated in the high-speed mode of operation, and reconfiguring the physical interface in response to the second code word, such that it operates in the low-power mode of operation. The first code word, the second code word, and the data may be transmitted in signals bound by a common voltage range. In one example, the voltage range is less than 600 millivolts.

公开(公告)号：US09582457B2

公开(公告)日：2017-02-28

申请号：US14302365

申请日：2014-06-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: G06F13/42 ,  G06F13/364 ,  H04L7/033

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

Abstract: System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation.

Abstract translation: 描述了包括串行总线的系统，方法和装置，其包括用于互联集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线。 总线具有第一线路和第二线路，耦合到总线的第一组设备和耦合到总线的第二组设备。 操作总线的方法包括配置第一组设备以使用第一行进行数据传输，并且在第一操作模式中使用第二行作为第一时钟信号，并且将第二组设备配置为使用第一组 线和用于数据传输的第二行，同时在第二操作模式中将第二时钟信号嵌入在数据传输的符号转换内。

公开(公告)号：US20170041130A1

公开(公告)日：2017-02-09

申请号：US15270853

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Ohjoon Kwon

IPC: H04L7/00 ,  H04L27/227 ,  H04L27/00 ,  H04L27/20

CPC classification number: H04L7/0087 ,  H04B1/40 ,  H04L7/0083 ,  H04L25/14 ,  H04L25/4923 ,  H04L27/0002 ,  H04L27/20 ,  H04L27/227

Abstract: Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 两个集成电路（IC）器件可以并置在电子设备中并且通过3线，3相接口通信耦合。 在两个或更多个设备中的第一个上可操作的数据传输方法包括确定存在涉及两条或更多条导线的3线通信链路的未对准，并且反转信令转换中编码的3位符号的第一位 当确定3线通信链路的未对准被确定为影响在三条线路上承载的两个或更多个信号之间的相位关系时，3线通信链路的状态，使得反转第一比特校正两个或更多个之间的相位关系 信号。 三相信号的版本可以通过三条线中的每一条在不同的相位状态下传送。

公开(公告)号：US09497710B2

公开(公告)日：2016-11-15

申请号：US14089550

申请日：2013-11-25

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Olaf Josef Hirsch ,  Richard Dominic Wietfeldt

IPC: H04W52/18 ,  H04W88/02 ,  H04W52/54 ,  H04L12/413 ,  H04L12/40

CPC classification number: H04W52/18 ,  H04L12/4015 ,  H04L12/413 ,  H04W52/54 ,  H04W88/02

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Each device can contend for control of a communications link by driving a data signal to a first voltage level. If the data signal or a clock signal changes before an arbitration time period has elapsed, one or more devices yield control of the communications link to another contender. The arbitration time period for each contender is different and indicates a priority of the message to be transmitted. A shorter arbitration time period indicates higher priority. Arbitration may commence after clock and data signals of the communications link remain in an idle or other predefined state for a minimum idle time. The minimum idle time may be different for different nodes and may be shorter for high priority messages or nodes.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 每个设备可以通过将数据信号驱动到第一电压电平来争取控制通信链路。 如果在仲裁时间段过去之前数据信号或时钟信号改变，则一个或多个设备产生对另一个竞争者的通信链路的控制。 每个竞争者的仲裁时间段不同，表示要发送的消息的优先级。 较短的仲裁时间段表示优先级较高。 仲裁可以在通信链路的时钟和数据信号保持在空闲或其他预定义状态中达到最小空闲时间之后开始。 不同节点的最小空闲时间可能不同，对于高优先级消息或节点可能较短。

公开(公告)号：US20160162423A1

公开(公告)日：2016-06-09

申请号：US15041901

申请日：2016-02-11

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36 ,  G06F13/4063 ,  G06F13/4068 ,  G06F13/4278 ,  G06F13/4282 ,  H04L7/0033 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/4919 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

公开(公告)号：US09276731B2

公开(公告)日：2016-03-01

申请号：US14453346

申请日：2014-08-06

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley

IPC: H04L7/00 ,  G06F13/42 ,  H04L25/49

CPC classification number: G06F13/36 ,  G06F13/4063 ,  G06F13/4068 ,  G06F13/4278 ,  G06F13/4282 ,  H04L7/0033 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/4919 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 驱动器可以被适配或配置成在两个或更多个连接器上对准状态转换，以使连续符号之间的过渡周期最小化。 驱动器可以包括推进或延迟某些转换的电路。 驱动器可以包括预加重电路，即，即使当连接器转换到未驱动状态时，该预加重电路用于驱动连接器的一部分过渡期的状态。

公开(公告)号：US09231790B2

公开(公告)日：2016-01-05

申请号：US14090625

申请日：2013-11-26

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Glenn Raskin ,  Chulkyu Lee

IPC: G06F15/16 ,  H04L25/02 ,  H04L5/20 ,  H04L25/49

CPC classification number: H04L25/0272 ,  H04L5/20 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L25/4917

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 数据以多位符号编码，并且多位符号在多个连接器上传输。 可以通过将符号映射到多个连接器的状态序列来传输多比特符号，并且根据状态序列来驱动连接器。 状态序列的定时可以在连续状态之间的每个转换处在接收器处确定。 每个连接器的状态可以由在每个连接器上传输的多相信号的极性和旋转方向来定义。

公开(公告)号：US09118457B2

公开(公告)日：2015-08-25

申请号：US14205242

申请日：2014-03-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: H04L7/00 ,  H04L7/027 ,  G06F13/40 ,  G06F13/42 ,  H04L25/14

CPC classification number: H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。

公开(公告)号：US09083598B2

公开(公告)日：2015-07-14

申请号：US13826546

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04L25/34 ,  H04L25/49 ,  H04L5/20 ,  H04L25/02

CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract translation: 提供了高速串行接口。 一方面，高速串行接口使用三相调制来共同编码数据和时钟信息。 因此，消除了在接口的接收端处对偏斜电路的需要，从而减少了链路启动时间，并提高了链路效率和功耗。 在一个实施例中，高速串行接口使用比具有用于数据和时钟信息的单独导体的传统系统更少的信号导体。 在另一个实施例中，串行接口允许以任何速度发送数据，而没有接收端具有传输数据速率的先前知识。 另一方面，高速串行接口使用极性编码的三相调制来共同编码数据和时钟信息。 这进一步增加了串行接口的链路容量，允许在任何单个波特率间隔内传输多于一个位。

公开(公告)号：US08970248B2

公开(公告)日：2015-03-03

申请号：US14210246

申请日：2014-03-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H03K17/16 ,  H04L27/20 ,  G06F13/40 ,  G08C19/00 ,  H04B1/06 ,  H04B3/00 ,  H04L25/02 ,  H04L29/06

CPC classification number: H04L27/2071 ,  G06F13/4063 ,  G08C19/00 ,  H04B1/06 ,  H04B3/00 ,  H04L25/0272 ,  H04L25/0292 ,  H04L69/18

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract translation: 提供用于接收机设备的终端网络以支持D-PHY信令和N阶因子信令。 多个动态可配置开关中的每一个的第一端耦合到公共节点。 多个电阻中的每一个的第一端耦合到相应开关的第二端。 多个端子接收差分信号，并且每个端子耦合到电阻的对应的第二端。 多个差分接收器中的每一个耦合在终端网络的两个终端之间，其中第一差分接收机和第二差分接收机耦合到相同的两个终端，当差分信号使用第一类型的差分时，使用第一差分接收机 信号编码时，当差分信号使用第二类型的差分信号编码时，使用第二差分接收机。