公开(公告)号：US12074648B2

公开(公告)日：2024-08-27

申请号：US17950093

申请日：2022-09-21

Applicant: QUALCOMM Incorporated

Inventor： Erwin Spits ,  Francesco Gatta ,  Adrianus Van Bezooijen ,  Leon Metreaud ,  Hakan Inanoglu

IPC: H04B17/00 ,  H04B17/12 ,  H04B17/13 ,  H04B17/21

CPC classification number: H04B17/0085 ,  H04B17/12 ,  H04B17/13 ,  H04B17/21

Abstract: A wireless communication device is provided with an in-device capability of characterizing the coupling between a pair of antennas. The wireless communication device determines the coupling through an operating gain measurement and through calibration gain measurements obtained through test ports.

公开(公告)号：US11962278B2

公开(公告)日：2024-04-16

申请号：US17318959

申请日：2021-05-12

Applicant: QUALCOMM Incorporated

Inventor： Ahmed Abbas Mohamed Helmy ,  Mehran Bakhshiani ,  Francesco Gatta ,  Hasnain Lakdawala ,  Rahul Karmaker ,  Shankar Guhados

IPC: H03F3/45 ,  H03G3/30 ,  H03H11/12 ,  H03H19/00 ,  H04B1/00 ,  H04B1/16 ,  H04B1/18

CPC classification number: H03F3/45475 ,  H03G3/30 ,  H03H11/1226 ,  H03H19/004 ,  H04B1/0032 ,  H04B1/0039 ,  H04B1/0042 ,  H04B1/0078 ,  H04B1/1615 ,  H04B1/18 ,  H03F2200/129 ,  H03F2200/165 ,  H03F2203/45526

Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

公开(公告)号：US11863140B2

公开(公告)日：2024-01-02

申请号：US17318968

申请日：2021-05-12

Applicant: QUALCOMM Incorporated

Inventor： Ahmed Abbas Mohamed Helmy ,  Mehran Bakhshiani ,  Francesco Gatta

IPC: H04L27/06 ,  H03F3/45 ,  H03G3/30 ,  H03H11/12 ,  H03H19/00 ,  H04B1/00 ,  H04B1/16 ,  H04B1/18

CPC classification number: H03F3/45475 ,  H03G3/30 ,  H03H11/1226 ,  H03H19/004 ,  H04B1/0032 ,  H04B1/0039 ,  H04B1/0042 ,  H04B1/0078 ,  H04B1/1615 ,  H04B1/18 ,  H03F2200/129 ,  H03F2200/165 ,  H03F2203/45526

Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and merging at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

公开(公告)号：US11184039B1

公开(公告)日：2021-11-23

申请号：US16882313

申请日：2020-05-22

Applicant: QUALCOMM Incorporated

Inventor： Rahul Karmaker ,  Francesco Gatta

IPC: H04B1/00 ,  H04B1/06 ,  H04B1/04

Abstract: According to certain aspects, a chip includes a first port, a first amplifier, and a first input path coupling the first port to an input of the first amplifier. The chip also includes a second port, a second amplifier, and a second input path coupling the second port to an input of the second amplifier. The chip further includes a switchable path coupled between the first input path and the second input path.

公开(公告)号：US09893875B2

公开(公告)日：2018-02-13

申请号：US15270444

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Marco Zanuso ,  Mohammad Elbadry ,  Tsai-Pi Hung ,  Ravi Sridhara ,  Francesco Gatta ,  Jingcheng Zhuang

IPC: H03D3/24 ,  H04L7/033 ,  H04L29/06 ,  H04L5/14 ,  H03L7/14 ,  H03L7/197 ,  H04W84/04

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.