公开(公告)号：US09990328B2

公开(公告)日：2018-06-05

申请号：US14959006

申请日：2015-12-04

Applicant: QUALCOMM Incorporated

Inventor： Nir Gerber ,  Itamar Berman ,  Yair Shmuel Cassuto ,  Terrence Brian Remple

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/382 ,  G06F13/385

Abstract: Two super-speed lanes may be enabled on a single USB cable. In an exemplary, non-limiting aspect, the USB cable is a Type-C cable. In further non-limiting aspects, the super-speed lanes may be present even if there is no USB 2.0 lane present on the D+/D− pins of the USB cable. Use of the second super-speed lane increases data throughput. Eliminating the requirement that the D+/D− pins be used for USB 2.0 data allows greater flexibility in the use of the USB connection because audio or video data may be sent over the D+/D− pins instead of USB 2.0 data. Further, the use of the two super-speed lanes allows a single computing element to operate as a host on one lane and a device on a second lane.

公开(公告)号：US09736521B2

公开(公告)日：2017-08-15

申请号：US14556491

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Dafna Shaool ,  Nir Gerber ,  Liat Bonen

IPC: H04N7/167 ,  H04N21/41 ,  H04N21/8547 ,  H04N21/43 ,  H04N21/434 ,  H04N21/418 ,  H04N21/443 ,  H04N21/4363 ,  H04N21/44 ,  H04N21/426 ,  H04N21/61 ,  H04H60/15

CPC classification number: H04N21/4104 ,  H04H60/15 ,  H04N21/4181 ,  H04N21/42623 ,  H04N21/4305 ,  H04N21/4343 ,  H04N21/43632 ,  H04N21/44004 ,  H04N21/4436 ,  H04N21/6143 ,  H04N21/8547 ,  Y02D70/168

Abstract: Systems, methods, devices, and non-transitory media of the various embodiments facilitate real time playback of a digital broadcast by enabling reduction of the amount of time a receiver device's low power mode interface with a separate computing device operates in an operational/high power mode. The receiver device may associate a stream of media packets of a digital broadcast with system time clock timestamps indicating when the media packets were received, and store the media packets in a temporary packet buffer. Periodically, a media packet burst stored in the temporary packet buffer may be sent to the separate computing device via a low power mode interface operating in an operational/high-power mode different than a low power mode. The low power mode interface may be returned to the low-power mode until the next burst of packets is sent to the separate computing device.

公开(公告)号：US20160320823A1

公开(公告)日：2016-11-03

申请号：US14702175

申请日：2015-05-01

Applicant: QUALCOMM Incorporated

Inventor： Nir Gerber ,  Lior Amarilio ,  Amit Gil

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3253 ,  G06F13/385 ,  G06F2213/0042 ,  Y02D10/151 ,  Y02D50/20

Abstract: Aspects disclosed in the detailed description include scheduled universal serial bus (USB) low-power operations. In this regard, in one aspect, a USB host controller determines a low-power operation schedule for a USB client device. The low-power operation schedule comprises one or more scheduled low-power operation periods, each corresponding to a respective entry time and a respective exit time. The USB host controller communicates the low-power operation schedule to the USB client device using one or more USB standard packets. By scheduling the one or more scheduled low-power operation periods with respective entry and exit times, the USB host controller or the USB client controller is able to start and end the one or more scheduled low-power operation periods without incurring additional signaling, thus improving efficiency of the USB low-power operation. Further, by communicating the low-power operation schedule using USB standard packets, it is possible to preserve compatibility with USB standards.

Abstract translation: 在详细描述中公开的方面包括调度的通用串行总线（USB）低功率操作。 在这方面，在一方面，USB主机控制器确定USB客户端设备的低功率操作调度。 低功率操作调度包括一个或多个调度的低功率操作周期，每个周期对应于相应的进入时间和相应的退出时间。 USB主机控制器使用一个或多个USB标准数据包将低功耗操作计划传送到USB客户端设备。 通过调度具有相应进入和退出时间的一个或多个调度的低功率操作时段，USB主机控制器或USB客户端控制器能够开始和结束一个或多个调度的低功率操作时段，而不会产生额外的信号，因此 提高USB低功耗操作的效率。 此外，通过使用USB标准分组传送低功率运行调度表，可以保持与USB标准的兼容性。

公开(公告)号：US20160210254A1

公开(公告)日：2016-07-21

申请号：US14598325

申请日：2015-01-16

Applicant: QUALCOMM Incorporated

Inventor： Nabeel Achlaug ,  Nir Gerber ,  Sergio Kolor ,  Dan Vardi

IPC: G06F13/38

CPC classification number: G06F13/385 ,  G06F13/4291 ,  G06F13/4295 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: Fast link training in embedded systems is disclosed. In one aspect, a host takes advantage of situations in which the host is coupled to one or more static devices through a communication bus. In particular, because the one or more devices are static, the host may be provided with information about the one or more devices before start up, so that when the host does perform a start up, the host already knows which device(s) to expect. Accordingly, the host may directly query the expected device(s), and after receipt of response(s) from the expected device(s), may begin link training the expected device(s). By using the provided information about the expected device(s) in this fashion, the host may bypass or skip an initial signal detection step used by conventional link training processes. Bypassing the initial signal detection step may save time, which in turn saves power.

Abstract translation: 披露了嵌入式系统中的快速链接训练。 在一个方面，主机利用主机通过通信总线耦合到一个或多个静态设备的情况。 特别地，因为一个或多个设备是静态的，所以主机可以在启动之前被提供关于一个或多个设备的信息，使得当主机执行启动时，主机已经知道哪个设备 期望。 因此，主机可以直接查询所期望的设备，并且在从预期设备接收到响应之后，可以开始链接训练期望的设备。 通过以这种方式使用关于预期设备的提供的信息，主机可以绕过或跳过常规链路训练过程所使用的初始信号检测步骤。 绕过初始信号检测步骤可以节省时间，从而节省电力。

公开(公告)号：US20160088554A1

公开(公告)日：2016-03-24

申请号：US14491175

申请日：2014-09-19

Applicant: QUALCOMM Incorporated

Inventor： Fernando Igartua ,  Nir Gerber

IPC: H04W52/02 ,  H04W4/00 ,  G06F13/42

CPC classification number: H04W52/0209 ,  G06F13/4221 ,  H04B1/123 ,  H04B15/02 ,  H04W4/80 ,  H04W88/06 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/168 ,  Y02D70/40

Abstract: Aspects of priority arbitration for interference mitigation are disclosed. In one aspect, a computing device is provided that employs a control system configured to arbitrate the activity of multiple interfaces. This arbitration mitigates potential electromagnetic interference (EMI) that may degrade the performance of the computing device. Upon a first interface requesting to become active, the control system is configured to determine if a second interface is currently active. If so, the control system is configured to arbitrate the activity of the first interface and the second interface to mitigate the potential EMI generated if the interfaces are concurrently active. The computing device includes an aggressor controller and a victim receiver, each corresponding to a particular interface. The control system is configured to arbitrate such activity so that the aggressor controller and corresponding cable do not generate EMI during a time period that would degrade the performance of the victim receiver.

Abstract translation: 披露干扰缓解优先仲裁方面。 在一个方面，提供了一种计算设备，其使用被配置为仲裁多个接口的活动的控制系统。 该仲裁减轻了可能降低计算设备性能的潜在电磁干扰（EMI）。 在第一接口请求激活时，控制系统被配置为确定第二接口当前是否处于活动状态。 如果是这样，则控制系统被配置为对第一接口和第二接口的活动进行仲裁以减轻如果接口同时处于活动状态时产生的潜在EMI。 计算设备包括攻击者控制器和受害者接收器，每个对应于特定接口。 控制系统被配置为仲裁这样的活动，使得攻击者控制器和相应的电缆在会降低受害者接收者的性能的时间段期间不产生EMI。

公开(公告)号：US20150149841A1

公开(公告)日：2015-05-28

申请号：US14087047

申请日：2013-11-22

Applicant: QUALCOMM Incorporated

Inventor： Nir Gerber

IPC: G11C29/50 ,  G06F13/28

CPC classification number: G11C29/50004 ,  G06F13/28 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods for low voltage secure digital (SD) interfaces are disclosed. Embodiments of the present disclosure relate to systems and voltage for a lower voltage SD or SD Input/Output (SDIO) interface such as two integrated circuits. In particular, a SD or SDIO interface may be established between two SD compliant devices. While the SD compliant devices may otherwise comply with the SD standard, the voltage levels for signals passed between the SD compliant devices may be below 1.8 volts that the standard mandates. This reduced voltage is possible because the distances involved for interchip communication or the short distances involved for mobile terminal to peripheral connection are short enough that the reduced voltage is sufficient to still provide the desired signal strength at the receiver.

Abstract translation: 公开了用于低压安全数字（SD）接口的系统和方法。 本公开的实施例涉及用于诸如两个集成电路的较低电压SD或SD输入/输出（SDIO）接口的系统和电压。 特别地，可以在两个SD兼容设备之间建立SD或SDIO接口。 虽然符合SD标准的设备可能会符合SD标准，但在SD兼容设备之间通过的信号的电压电平可能低于标准要求的1.8伏。 这种降低的电压是可能的，因为用于芯片间通信所涉及的距离或移动终端到外围连接涉及的短距离足够短，使得降低的电压足以在接收器处仍然提供期望的信号强度。